From 3a1babe3660938ebcf8f2054b4c38be71b48dce2 Mon Sep 17 00:00:00 2001
From: Laszlo Nagy <laszlo.nagy@analog.com>
Date: Tue, 21 Sep 2021 07:33:27 +0100
Subject: [PATCH] ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock

Reset transceiver with a pulse
---
 .../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl    |  4 +++-
 projects/ad9081_fmca_ebz/vck190/system_top.v         | 12 +++++++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
index 3d223f74b..915451604 100644
--- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -137,6 +137,8 @@ if {$ADI_PHY_SEL == 1} {
 
   create_bd_cell -type container -reference jesd_phy jesd204_phy
 
+  create_bd_port -dir I gt_reset
+
 }
 
 if {$ADI_PHY_SEL == 1} {
@@ -322,7 +324,7 @@ if {$ADI_PHY_SEL == 1} {
   ad_connect GND jesd204_phy/reset_rx_pll_and_datapath_in
   ad_connect GND jesd204_phy/reset_tx_pll_and_datapath_in
 
-  ad_connect GND jesd204_phy/gt_reset_gt_bridge_ip_0
+  ad_connect gt_reset jesd204_phy/gt_reset_gt_bridge_ip_0
 
   ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy/reset_rx_datapath_in
   ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy/reset_tx_datapath_in
diff --git a/projects/ad9081_fmca_ebz/vck190/system_top.v b/projects/ad9081_fmca_ebz/vck190/system_top.v
index d98d23ad9..eb6accfb1 100644
--- a/projects/ad9081_fmca_ebz/vck190/system_top.v
+++ b/projects/ad9081_fmca_ebz/vck190/system_top.v
@@ -219,6 +219,15 @@ module system_top  #(
   assign gpio_i[94:54] = gpio_o[94:54];
   assign gpio_i[31:10] = gpio_o[31:10];
 
+  reg ext_pll_lock,ext_pll_lock_d;
+
+  always @(posedge tx_device_clk) begin
+    ext_pll_lock <= gpio_i[43];
+    ext_pll_lock_d <= ext_pll_lock;
+  end
+
+  assign gt_reset = ext_pll_lock & ~ext_pll_lock_d;
+
   system_wrapper i_system_wrapper (
     .gpio0_i (gpio_i[31:0]),
     .gpio0_o (gpio_o[31:0]),
@@ -268,7 +277,8 @@ module system_top  #(
     .rx_sync_0 (rx_syncout),
     .tx_sync_0 (tx_syncin),
     .rx_sysref_0 (sysref),
-    .tx_sysref_0 (sysref)
+    .tx_sysref_0 (sysref),
+    .gt_reset (gt_reset)
   );
 
   assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];