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axi-xcvr: removed xcvr compoents

main
Rejeesh Kutty 2015-07-21 10:56:04 -04:00
parent 264f9ffbfc
commit 3a4581a8df
3 changed files with 114 additions and 69 deletions
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138
library/axi_jesd_xcvr/axi_jesd_xcvr.v
View File

@ -39,26 +39,39 @@
module axi_jesd_xcvr ( module axi_jesd_xcvr (
rst,
// receive interface // receive interface
rx_ref_clk,
rx_d,
rx_clk, rx_clk,
rx_rstn,
rx_ext_sysref_in, rx_ext_sysref_in,
rx_ext_sysref_out, rx_ext_sysref_out,
rx_sync, rx_sync,
rx_sof, rx_sof,
rx_data, rx_data,
rx_ready,
rx_ip_sysref,
rx_ip_sync,
rx_ip_sof,
rx_ip_valid,
rx_ip_data,
rx_ip_ready,
// transmit interface // transmit interface
tx_ref_clk,
tx_d,
tx_clk, tx_clk,
tx_rstn,
tx_ext_sysref_in, tx_ext_sysref_in,
tx_ext_sysref_out, tx_ext_sysref_out,
tx_sync, tx_sync,
tx_data, tx_data,
tx_ready,
tx_ip_sysref,
tx_ip_sync,
tx_ip_valid,
tx_ip_data,
tx_ip_ready,
// axi-lite (slave) // axi-lite (slave)
@ -89,26 +102,39 @@ module axi_jesd_xcvr (
parameter PCORE_NUM_OF_TX_LANES = 4; parameter PCORE_NUM_OF_TX_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4; parameter PCORE_NUM_OF_RX_LANES = 4;
output rst;
// receive interface // receive interface
input rx_ref_clk; input rx_clk;
input [(PCORE_NUM_OF_RX_LANES-1):0] rx_d; output rx_rstn;
output rx_clk;
input rx_ext_sysref_in; input rx_ext_sysref_in;
output rx_ext_sysref_out; output rx_ext_sysref_out;
output rx_sync; output rx_sync;
output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_sof; output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_sof;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data; output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_ready;
output rx_ip_sysref;
input rx_ip_sync;
input [ 3:0] rx_ip_sof;
input rx_ip_valid;
input [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data;
output rx_ip_ready;
// transmit interface // transmit interface
input tx_ref_clk; input tx_clk;
output [(PCORE_NUM_OF_TX_LANES-1):0] tx_d; output tx_rstn;
output tx_clk;
input tx_ext_sysref_in; input tx_ext_sysref_in;
output tx_ext_sysref_out; output tx_ext_sysref_out;
input tx_sync; input tx_sync;
input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_data; input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_data;
input [((PCORE_NUM_OF_RX_LANES* 1)-1):0] tx_ready;
output tx_ip_sysref;
output tx_ip_sync;
output tx_ip_valid;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] tx_ip_data;
input tx_ip_ready;
// axi interface // axi interface
@ -139,17 +165,9 @@ module axi_jesd_xcvr (
wire up_rstn; wire up_rstn;
wire up_clk; wire up_clk;
wire [ 7:0] status_s; wire [ 7:0] status_s;
wire rst; wire [ 3:0] rx_ip_sof_s;
wire rx_rstn;
wire rx_ip_sync_s;
wire [ 3:0] rx_ip_sof_s;
wire [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data_s; wire [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data_s;
wire [(PCORE_NUM_OF_RX_LANES-1):0] rx_ready_s;
wire [ 7:0] rx_status_s; wire [ 7:0] rx_status_s;
wire tx_rstn;
wire tx_ip_sync_s;
wire [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_ip_data_s;
wire [(PCORE_NUM_OF_TX_LANES-1):0] tx_ready_s;
wire [ 7:0] tx_status_s; wire [ 7:0] tx_status_s;
wire up_wreq_s; wire up_wreq_s;
wire [ 13:0] up_waddr_s; wire [ 13:0] up_waddr_s;
@ -159,34 +177,45 @@ module axi_jesd_xcvr (
wire [ 13:0] up_raddr_s; wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s; wire [ 31:0] up_rdata_s;
wire up_rack_s; wire up_rack_s;
// variables
genvar n;
// assignments // assignments
assign status_s = 8'hff; assign status_s = 8'hff;
assign up_rstn = s_axi_aresetn; assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk; assign up_clk = s_axi_aclk;
assign rx_ip_ready = 1'b1;
assign rx_ip_sysref = rx_ext_sysref_out;
assign rx_ip_sof_s[3] = rx_ip_sof[0];
assign rx_ip_sof_s[2] = rx_ip_sof[1];
assign rx_ip_sof_s[1] = rx_ip_sof[2];
assign rx_ip_sof_s[0] = rx_ip_sof[3];
generate generate
if (PCORE_NUM_OF_TX_LANES < 8) begin for (n = 0; n < PCORE_NUM_OF_RX_LANES; n = n + 1) begin: g_rx_swap
assign tx_status_s[7:PCORE_NUM_OF_TX_LANES] = status_s[7:PCORE_NUM_OF_TX_LANES]; assign rx_ip_data_s[((n*32) + 31):((n*32) + 24)] = rx_ip_data[((n*32) + 7):((n*32) + 0)];
assign tx_status_s[(PCORE_NUM_OF_TX_LANES-1):0] = tx_ready_s; assign rx_ip_data_s[((n*32) + 23):((n*32) + 16)] = rx_ip_data[((n*32) + 15):((n*32) + 8)];
end else begin assign rx_ip_data_s[((n*32) + 15):((n*32) + 8)] = rx_ip_data[((n*32) + 23):((n*32) + 16)];
assign tx_status_s = tx_ready_s[7:0]; assign rx_ip_data_s[((n*32) + 7):((n*32) + 0)] = rx_ip_data[((n*32) + 31):((n*32) + 24)];
end end
endgenerate endgenerate
generate generate
if (PCORE_NUM_OF_RX_LANES < 8) begin if (PCORE_NUM_OF_RX_LANES < 8) begin
assign rx_status_s[7:PCORE_NUM_OF_RX_LANES] = status_s[7:PCORE_NUM_OF_RX_LANES]; assign rx_status_s[7:PCORE_NUM_OF_RX_LANES] = status_s[7:PCORE_NUM_OF_RX_LANES];
assign rx_status_s[(PCORE_NUM_OF_RX_LANES-1):0] = rx_ready_s; assign rx_status_s[(PCORE_NUM_OF_RX_LANES-1):0] = rx_ready;
end else begin end else begin
assign rx_status_s = rx_ready_s[7:0]; assign rx_status_s = rx_ready[7:0];
end end
endgenerate endgenerate
genvar n;
generate generate
for (n = 0; n < PCORE_NUM_OF_RX_LANES; n = n + 1) begin: g_rx_lane for (n = 0; n < PCORE_NUM_OF_RX_LANES; n = n + 1) begin: g_rx_align
ad_jesd_align i_jesd_align ( ad_jesd_align i_jesd_align (
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof_s), .rx_ip_sof (rx_ip_sof_s),
@ -196,41 +225,26 @@ module axi_jesd_xcvr (
end end
endgenerate endgenerate
assign tx_ip_valid = 1'b1;
assign tx_ip_sysref = tx_ext_sysref_out;
generate generate
for (n = 0; n < PCORE_NUM_OF_TX_LANES; n = n + 1) begin: g_tx_lane for (n = 0; n < PCORE_NUM_OF_TX_LANES; n = n + 1) begin: g_tx_swap
assign tx_ip_data_s[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)]; assign tx_ip_data[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)];
assign tx_ip_data_s[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)]; assign tx_ip_data[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)];
assign tx_ip_data_s[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)]; assign tx_ip_data[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)];
assign tx_ip_data_s[((n*32) + 7):((n*32) + 0)] = tx_data[((n*32) + 31):((n*32) + 24)]; assign tx_ip_data[((n*32) + 7):((n*32) + 0)] = tx_data[((n*32) + 31):((n*32) + 24)];
end end
endgenerate endgenerate
sys_xcvr #( generate
.PCORE_NUM_OF_TX_LANES (PCORE_NUM_OF_TX_LANES), if (PCORE_NUM_OF_TX_LANES < 8) begin
.PCORE_NUM_OF_RX_LANES (PCORE_NUM_OF_RX_LANES)) assign tx_status_s[7:PCORE_NUM_OF_TX_LANES] = status_s[7:PCORE_NUM_OF_TX_LANES];
i_sys_xcvr ( assign tx_status_s[(PCORE_NUM_OF_TX_LANES-1):0] = tx_ready;
.up_clk (up_clk), end else begin
.up_rstn (up_rstn), assign tx_status_s = tx_ready[7:0];
.rx_ref_clk (rx_ref_clk), end
.rx_d (rx_d), endgenerate
.tx_ref_clk (tx_ref_clk),
.tx_d (tx_d),
.rst (rst),
.rx_clk (rx_clk),
.rx_rstn (rx_rstn),
.rx_sysref (rx_ext_sysref_out),
.rx_ip_sync (rx_ip_sync_s),
.rx_ip_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s),
.rx_ready (rx_ready_s),
.rx_int (),
.tx_clk (tx_clk),
.tx_rstn (tx_rstn),
.tx_sysref (tx_ext_sysref_out),
.tx_ip_sync (tx_ip_sync_s),
.tx_ip_data (tx_ip_data_s),
.tx_ready (tx_ready_s),
.tx_int ());
// processor // processor
@ -243,7 +257,7 @@ module axi_jesd_xcvr (
.rx_rstn (rx_rstn), .rx_rstn (rx_rstn),
.rx_ext_sysref (rx_ext_sysref_in), .rx_ext_sysref (rx_ext_sysref_in),
.rx_sysref (rx_ext_sysref_out), .rx_sysref (rx_ext_sysref_out),
.rx_ip_sync (rx_ip_sync_s), .rx_ip_sync (rx_ip_sync),
.rx_sync (rx_sync), .rx_sync (rx_sync),
.rx_status (rx_status_s), .rx_status (rx_status_s),
.tx_clk (tx_clk), .tx_clk (tx_clk),
@ -251,7 +265,7 @@ module axi_jesd_xcvr (
.tx_ext_sysref (tx_ext_sysref_in), .tx_ext_sysref (tx_ext_sysref_in),
.tx_sysref (tx_ext_sysref_out), .tx_sysref (tx_ext_sysref_out),
.tx_sync (tx_sync), .tx_sync (tx_sync),
.tx_ip_sync (tx_ip_sync_s), .tx_ip_sync (tx_ip_sync),
.tx_status (tx_status_s), .tx_status (tx_status_s),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),

1
library/axi_jesd_xcvr/axi_jesd_xcvr_constr.sdc
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@ -1,5 +1,4 @@
set_false_path -from [get_registers *preset*] -to [get_registers *rst*]
set_false_path -from [get_registers *up_rx_*] -to [get_registers *rx_*] set_false_path -from [get_registers *up_rx_*] -to [get_registers *rx_*]
set_false_path -from [get_registers *up_tx_*] -to [get_registers *tx_*] set_false_path -from [get_registers *up_tx_*] -to [get_registers *tx_*]
set_false_path -from [get_registers *rx_sync*] -to [get_registers *up_rx_status_m1*] set_false_path -from [get_registers *rx_sync*] -to [get_registers *up_rx_status_m1*]

44
library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
View File

@ -9,6 +9,7 @@ set_module_property DESCRIPTION "AXI JESD XCVR Interface"
set_module_property VERSION 1.0 set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices" set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_jesd_xcvr set_module_property DISPLAY_NAME axi_jesd_xcvr
set_module_property ELABORATION_CALLBACK p_axi_jesd_xcvr
# files # files
@ -85,20 +86,51 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface # transceiver interface
ad_alt_intf clock rx_ref_clk input 1 ad_alt_intf reset rst output 1 s_axi_clock s_axi_reset
ad_alt_intf signal rx_d input 4
ad_alt_intf clock rx_clk output 1 ad_alt_intf clock rx_clk input 1
ad_alt_intf reset-n rx_rstn output 1 if_rx_clk s_axi_reset
ad_alt_intf signal rx_ext_sysref_in input 1 ad_alt_intf signal rx_ext_sysref_in input 1
ad_alt_intf signal rx_ext_sysref_out output 1 ad_alt_intf signal rx_ext_sysref_out output 1
ad_alt_intf signal rx_sync output 1 ad_alt_intf signal rx_sync output 1
ad_alt_intf signal rx_sof output PCORE_NUM_OF_RX_LANES ad_alt_intf signal rx_sof output PCORE_NUM_OF_RX_LANES
ad_alt_intf signal rx_data output PCORE_NUM_OF_RX_LANES*32 data ad_alt_intf signal rx_data output PCORE_NUM_OF_RX_LANES*32 data
ad_alt_intf signal rx_ready input PCORE_NUM_OF_RX_LANES rx_ready
ad_alt_intf signal rx_ip_sysref output 1 export
ad_alt_intf signal rx_ip_sync input 1 export
ad_alt_intf signal rx_ip_sof input 4 export
ad_alt_intf clock tx_ref_clk input 1 add_interface if_rx_ip_avl avalon_streaming sink
ad_alt_intf signal tx_d output 4 add_interface_port if_rx_ip_avl rx_ip_data data input PCORE_NUM_OF_RX_LANES*32
ad_alt_intf clock tx_clk output 1 add_interface_port if_rx_ip_avl rx_ip_valid valid input 1
add_interface_port if_rx_ip_avl rx_ip_ready ready output 1
ad_alt_intf clock tx_clk input 1
ad_alt_intf reset-n tx_rstn output 1 if_tx_clk s_axi_reset
ad_alt_intf signal tx_ext_sysref_in input 1 ad_alt_intf signal tx_ext_sysref_in input 1
ad_alt_intf signal tx_ext_sysref_out output 1 ad_alt_intf signal tx_ext_sysref_out output 1
ad_alt_intf signal tx_sync input 1 ad_alt_intf signal tx_sync input 1
ad_alt_intf signal tx_data input PCORE_NUM_OF_TX_LANES*32 data ad_alt_intf signal tx_data input PCORE_NUM_OF_TX_LANES*32 data
ad_alt_intf signal tx_ready input PCORE_NUM_OF_TX_LANES tx_ready
ad_alt_intf signal tx_ip_sysref output 1 export
ad_alt_intf signal tx_ip_sync output 1 export
add_interface if_tx_ip_avl avalon_streaming source
add_interface_port if_tx_ip_avl tx_ip_data data output PCORE_NUM_OF_TX_LANES*32
add_interface_port if_tx_ip_avl tx_ip_valid valid output 1
add_interface_port if_tx_ip_avl tx_ip_ready ready input 1
proc p_axi_jesd_xcvr {} {
set p_num_of_rx_lanes [get_parameter_value "PCORE_NUM_OF_RX_LANES"]
set p_num_of_tx_lanes [get_parameter_value "PCORE_NUM_OF_TX_LANES"]
set_interface_property if_rx_ip_avl associatedClock if_rx_clk
set_interface_property if_rx_ip_avl associatedReset if_rx_rstn
set_interface_property if_rx_ip_avl dataBitsPerSymbol [expr ($p_num_of_rx_lanes*32)]
set_interface_property if_tx_ip_avl associatedClock if_tx_clk
set_interface_property if_tx_ip_avl associatedReset if_tx_rstn
set_interface_property if_tx_ip_avl dataBitsPerSymbol [expr ($p_num_of_tx_lanes*32)]
}