diff --git a/library/axi_pulse_gen/axi_pulse_gen_regmap.v b/library/axi_pulse_gen/axi_pulse_gen_regmap.v
index 947b32bf5..7b95b1fe0 100644
--- a/library/axi_pulse_gen/axi_pulse_gen_regmap.v
+++ b/library/axi_pulse_gen/axi_pulse_gen_regmap.v
@@ -87,19 +87,19 @@ module axi_pulse_gen_regmap #(
       up_reset <= 1'b1;
     end else begin
       up_wack <= up_wreq;
-      if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h2)) begin
+      if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin
         up_scratch <= up_wdata;
       end
-      if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
+      if ((up_wreq == 1'b1) && (up_waddr == 14'h4)) begin
         up_reset <= up_wdata[0];
         up_load_config <= up_wdata[1];
       end else begin
         up_load_config <= 1'b0;
       end
-      if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
+      if ((up_wreq == 1'b1) && (up_waddr == 14'h5)) begin
         up_pulse_period <= up_wdata;
       end
-      if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
+      if ((up_wreq == 1'b1) && (up_waddr == 14'h6)) begin
         up_pulse_width <= up_wdata;
       end
     end
@@ -112,14 +112,14 @@ module axi_pulse_gen_regmap #(
     end else begin
       up_rack <= up_rreq;
       if (up_rreq == 1'b1) begin
-        case (up_raddr[3:0])
-          4'h0: up_rdata <= CORE_VERSION;
-          4'h1: up_rdata <= ID;
-          4'h2: up_rdata <= up_scratch;
-          4'h3: up_rdata <= CORE_MAGIC;
-          4'h4: up_rdata <= up_reset;
-          4'h5: up_rdata <= up_pulse_period;
-          4'h6: up_rdata <= up_pulse_width;
+        case (up_raddr)
+          14'h0: up_rdata <= CORE_VERSION;
+          14'h1: up_rdata <= ID;
+          14'h2: up_rdata <= up_scratch;
+          14'h3: up_rdata <= CORE_MAGIC;
+          14'h4: up_rdata <= up_reset;
+          14'h5: up_rdata <= up_pulse_period;
+          14'h6: up_rdata <= up_pulse_width;
           default: up_rdata <= 0;
         endcase
       end else begin