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axi_pulse_gen: Registers should be placed at front of the register space 

Because this register map will be integrated into other IPs too, make
sure that the registers are places in the absolute front of the register
space.
main
Istvan Csomortani 2019-03-20 12:12:49 +00:00 committed by István Csomortáni
parent 723f5cddfc
commit 3a7d0698a8
1 changed files with 12 additions and 12 deletions
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24
library/axi_pulse_gen/axi_pulse_gen_regmap.v
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@ -87,19 +87,19 @@ module axi_pulse_gen_regmap #(
up_reset <= 1'b1;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h2)) begin
if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin
up_scratch <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h4)) begin
if ((up_wreq == 1'b1) && (up_waddr == 14'h4)) begin
up_reset <= up_wdata[0];
up_load_config <= up_wdata[1];
end else begin
up_load_config <= 1'b0;
end
if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h5)) begin
if ((up_wreq == 1'b1) && (up_waddr == 14'h5)) begin
up_pulse_period <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[3:0] == 4'h6)) begin
if ((up_wreq == 1'b1) && (up_waddr == 14'h6)) begin
up_pulse_width <= up_wdata;
end
end
@ -112,14 +112,14 @@ module axi_pulse_gen_regmap #(
end else begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr[3:0])
4'h0: up_rdata <= CORE_VERSION;
4'h1: up_rdata <= ID;
4'h2: up_rdata <= up_scratch;
4'h3: up_rdata <= CORE_MAGIC;
4'h4: up_rdata <= up_reset;
4'h5: up_rdata <= up_pulse_period;
4'h6: up_rdata <= up_pulse_width;
case (up_raddr)
14'h0: up_rdata <= CORE_VERSION;
14'h1: up_rdata <= ID;
14'h2: up_rdata <= up_scratch;
14'h3: up_rdata <= CORE_MAGIC;
14'h4: up_rdata <= up_reset;
14'h5: up_rdata <= up_pulse_period;
14'h6: up_rdata <= up_pulse_width;
default: up_rdata <= 0;
endcase
end else begin