diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 8ab89abdf..edfcf6d1f 100755 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -50,10 +50,6 @@ module axi_ad9361 ( rx_data_in_p, rx_data_in_n, - // receive master/slave - adc_start_in, - adc_start_out, - // physical interface (transmit) tx_clk_out_p, @@ -74,6 +70,7 @@ module axi_ad9361 ( // dma interface + l_clk, clk, adc_dwr, @@ -112,7 +109,12 @@ module axi_ad9361 ( // monitor signals adc_mon_valid, - adc_mon_data); + adc_mon_data, + + // chipscope signals + + dev_dbg_data, + dev_l_dbg_data); // parameters @@ -134,10 +136,6 @@ module axi_ad9361 ( input [ 5:0] rx_data_in_p; input [ 5:0] rx_data_in_n; - // receive master/slave - input adc_start_in; - output adc_start_out; - // physical interface (transmit) output tx_clk_out_p; @@ -147,7 +145,8 @@ module axi_ad9361 ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; - // transmit master/slave + // master/slave + input dac_enable_in; output dac_enable_out; @@ -157,7 +156,9 @@ module axi_ad9361 ( // dma interface - output clk; + output l_clk; + + input clk; output adc_dwr; output [63:0] adc_ddata; output adc_dsync; @@ -196,6 +197,11 @@ module axi_ad9361 ( output adc_mon_valid; output [47:0] adc_mon_data; + // chipscope signals + + output [111:0] dev_dbg_data; + output [ 61:0] dev_l_dbg_data; + // internal registers reg [31:0] up_rdata = 'd0; @@ -294,6 +300,7 @@ module axi_ad9361 ( .tx_frame_out_n (tx_frame_out_n), .tx_data_out_p (tx_data_out_p), .tx_data_out_n (tx_data_out_n), + .l_clk (l_clk), .clk (clk), .adc_valid (adc_valid_s), .adc_data_i1 (adc_data_i1_s), @@ -317,8 +324,8 @@ module axi_ad9361 ( .delay_rdata (delay_rdata_s), .delay_ack_t (delay_ack_t_s), .delay_locked (delay_locked_s), - .dev_dbg_trigger (), - .dev_dbg_data ()); + .dev_dbg_data (dev_dbg_data), + .dev_l_dbg_data (dev_l_dbg_data)); // prbs/loopback interface @@ -378,8 +385,6 @@ module axi_ad9361 ( .adc_data_q2 (adc_data_q2_s), .adc_status (adc_status_s), .adc_r1_mode (adc_r1_mode_s), - .adc_start_in (adc_start_in), - .adc_start_out (adc_start_out), .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_sel (delay_sel_s), diff --git a/library/axi_ad9361/axi_ad9361_dev_if.v b/library/axi_ad9361/axi_ad9361_dev_if.v index 5f3178b43..b89a5045c 100755 --- a/library/axi_ad9361/axi_ad9361_dev_if.v +++ b/library/axi_ad9361/axi_ad9361_dev_if.v @@ -64,6 +64,7 @@ module axi_ad9361_dev_if ( // clock (common to both receive and transmit) clk, + l_clk, // receive data path interface @@ -98,8 +99,8 @@ module axi_ad9361_dev_if ( // chipscope signals - dev_dbg_trigger, - dev_dbg_data); + dev_dbg_data, + dev_l_dbg_data); // this parameter controls the buffer type based on the target device. @@ -128,7 +129,8 @@ module axi_ad9361_dev_if ( // clock (common to both receive and transmit) - output clk; + input clk; + output l_clk; // receive data path interface @@ -163,8 +165,8 @@ module axi_ad9361_dev_if ( // chipscope signals - output [ 3:0] dev_dbg_trigger; - output [297:0] dev_dbg_data; + output [111:0] dev_dbg_data; + output [ 61:0] dev_l_dbg_data; // internal registers @@ -184,6 +186,18 @@ module axi_ad9361_dev_if ( reg [11:0] rx_data_q1_r2 = 'd0; reg [11:0] rx_data_i2_r2 = 'd0; reg [11:0] rx_data_q2_r2 = 'd0; + reg adc_p_valid = 'd0; + reg [11:0] adc_p_data_i1 = 'd0; + reg [11:0] adc_p_data_q1 = 'd0; + reg [11:0] adc_p_data_i2 = 'd0; + reg [11:0] adc_p_data_q2 = 'd0; + reg adc_p_status = 'd0; + reg adc_n_valid = 'd0; + reg [11:0] adc_n_data_i1 = 'd0; + reg [11:0] adc_n_data_q1 = 'd0; + reg [11:0] adc_n_data_i2 = 'd0; + reg [11:0] adc_n_data_q2 = 'd0; + reg adc_n_status = 'd0; reg adc_valid = 'd0; reg [11:0] adc_data_i1 = 'd0; reg [11:0] adc_data_q1 = 'd0; @@ -198,6 +212,12 @@ module axi_ad9361_dev_if ( reg tx_frame = 'd0; reg [ 5:0] tx_data_p = 'd0; reg [ 5:0] tx_data_n = 'd0; + reg tx_n_frame = 'd0; + reg [ 5:0] tx_n_data_p = 'd0; + reg [ 5:0] tx_n_data_n = 'd0; + reg tx_p_frame = 'd0; + reg [ 5:0] tx_p_data_p = 'd0; + reg [ 5:0] tx_p_data_n = 'd0; reg [ 6:0] delay_ld = 'd0; reg [ 4:0] delay_rdata = 'd0; reg delay_ack_t = 'd0; @@ -224,60 +244,35 @@ module axi_ad9361_dev_if ( // device debug signals - assign dev_dbg_trigger[0] = rx_frame[0]; - assign dev_dbg_trigger[1] = rx_frame[1]; - assign dev_dbg_trigger[2] = tx_frame; - assign dev_dbg_trigger[3] = adc_status; - assign dev_dbg_data[ 5: 0] = tx_data_n; assign dev_dbg_data[ 11: 6] = tx_data_p; - assign dev_dbg_data[ 23: 12] = tx_data_i1_d; - assign dev_dbg_data[ 35: 24] = tx_data_q1_d; - assign dev_dbg_data[ 47: 36] = tx_data_i2_d; - assign dev_dbg_data[ 59: 48] = tx_data_q2_d; - assign dev_dbg_data[ 63: 60] = tx_data_sel_s; - assign dev_dbg_data[ 66: 64] = tx_data_cnt; - assign dev_dbg_data[ 67: 67] = tx_frame; - assign dev_dbg_data[ 68: 68] = dac_r1_mode; - assign dev_dbg_data[ 69: 69] = dac_valid; - assign dev_dbg_data[ 81: 70] = dac_data_i1; - assign dev_dbg_data[ 93: 82] = dac_data_q1; - assign dev_dbg_data[105: 94] = dac_data_i2; - assign dev_dbg_data[117:106] = dac_data_q2; - assign dev_dbg_data[118:118] = rx_frame_p_s; - assign dev_dbg_data[119:119] = rx_frame_n_s; - assign dev_dbg_data[120:120] = rx_frame_n; - assign dev_dbg_data[122:121] = rx_frame; - assign dev_dbg_data[124:123] = rx_frame_d; - assign dev_dbg_data[128:125] = rx_frame_s; - assign dev_dbg_data[134:129] = rx_data_p_s; - assign dev_dbg_data[140:135] = rx_data_n_s; - assign dev_dbg_data[146:141] = rx_data_n; - assign dev_dbg_data[158:147] = rx_data; - assign dev_dbg_data[170:159] = rx_data_d; - assign dev_dbg_data[171:171] = rx_error_r1; - assign dev_dbg_data[172:172] = rx_valid_r1; - assign dev_dbg_data[184:173] = rx_data_i_r1; - assign dev_dbg_data[196:185] = rx_data_q_r1; - assign dev_dbg_data[197:197] = rx_error_r2; - assign dev_dbg_data[198:198] = rx_valid_r2; - assign dev_dbg_data[210:199] = rx_data_i1_r2; - assign dev_dbg_data[222:211] = rx_data_q1_r2; - assign dev_dbg_data[234:223] = rx_data_i2_r2; - assign dev_dbg_data[246:235] = rx_data_q2_r2; - assign dev_dbg_data[247:247] = adc_r1_mode; - assign dev_dbg_data[248:248] = adc_status; - assign dev_dbg_data[249:249] = adc_valid; - assign dev_dbg_data[261:250] = adc_data_i1; - assign dev_dbg_data[273:262] = adc_data_q1; - assign dev_dbg_data[285:274] = adc_data_i2; - assign dev_dbg_data[297:286] = adc_data_q2; + assign dev_dbg_data[ 23: 12] = dac_data_i1; + assign dev_dbg_data[ 35: 24] = dac_data_q1; + assign dev_dbg_data[ 47: 36] = dac_data_i2; + assign dev_dbg_data[ 59: 48] = dac_data_q2; + assign dev_dbg_data[ 71: 60] = adc_data_i1; + assign dev_dbg_data[ 83: 72] = adc_data_q1; + assign dev_dbg_data[ 95: 84] = adc_data_i2; + assign dev_dbg_data[107: 96] = adc_data_q2; + assign dev_dbg_data[108:108] = tx_frame; + assign dev_dbg_data[109:109] = dac_valid; + assign dev_dbg_data[110:110] = adc_status; + assign dev_dbg_data[111:111] = adc_valid; + + assign dev_l_dbg_data[ 5: 0] = tx_p_data_n; + assign dev_l_dbg_data[ 11: 6] = tx_p_data_p; + assign dev_l_dbg_data[ 23: 12] = adc_p_data_i1; + assign dev_l_dbg_data[ 35: 24] = adc_p_data_q1; + assign dev_l_dbg_data[ 47: 36] = adc_p_data_i2; + assign dev_l_dbg_data[ 59: 48] = adc_p_data_q2; + assign dev_l_dbg_data[ 60: 60] = tx_p_frame; + assign dev_l_dbg_data[ 61: 61] = adc_p_valid; // receive data path interface assign rx_frame_s = {rx_frame_d, rx_frame}; - always @(posedge clk) begin + always @(posedge l_clk) begin rx_data_n <= rx_data_n_s; rx_frame_n <= rx_frame_n_s; rx_data <= {rx_data_n, rx_data_p_s}; @@ -288,7 +283,7 @@ module axi_ad9361_dev_if ( // receive data path for single rf, frame is expected to qualify i/q msb only - always @(posedge clk) begin + always @(posedge l_clk) begin rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1; rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0; if (rx_frame_s == 4'b1100) begin @@ -299,7 +294,7 @@ module axi_ad9361_dev_if ( // receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only - always @(posedge clk) begin + always @(posedge l_clk) begin rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1; rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0; @@ -315,24 +310,44 @@ module axi_ad9361_dev_if ( // receive data path mux - always @(posedge clk) begin + always @(posedge l_clk) begin if (adc_r1_mode == 1'b1) begin - adc_valid <= rx_valid_r1; - adc_data_i1 <= rx_data_i_r1; - adc_data_q1 <= rx_data_q_r1; - adc_data_i2 <= 12'd0; - adc_data_q2 <= 12'd0; - adc_status <= ~rx_error_r1; + adc_p_valid <= rx_valid_r1; + adc_p_data_i1 <= rx_data_i_r1; + adc_p_data_q1 <= rx_data_q_r1; + adc_p_data_i2 <= 12'd0; + adc_p_data_q2 <= 12'd0; + adc_p_status <= ~rx_error_r1; end else begin - adc_valid <= rx_valid_r2; - adc_data_i1 <= rx_data_i1_r2; - adc_data_q1 <= rx_data_q1_r2; - adc_data_i2 <= rx_data_i2_r2; - adc_data_q2 <= rx_data_q2_r2; - adc_status <= ~rx_error_r2; + adc_p_valid <= rx_valid_r2; + adc_p_data_i1 <= rx_data_i1_r2; + adc_p_data_q1 <= rx_data_q1_r2; + adc_p_data_i2 <= rx_data_i2_r2; + adc_p_data_q2 <= rx_data_q2_r2; + adc_p_status <= ~rx_error_r2; end end + // transfer to a synchronous common clock + + always @(negedge l_clk) begin + adc_n_valid <= adc_p_valid; + adc_n_data_i1 <= adc_p_data_i1; + adc_n_data_q1 <= adc_p_data_q1; + adc_n_data_i2 <= adc_p_data_i2; + adc_n_data_q2 <= adc_p_data_q2; + adc_n_status <= adc_p_status; + end + + always @(posedge clk) begin + adc_valid <= adc_n_valid; + adc_data_i1 <= adc_n_data_i1; + adc_data_q1 <= adc_n_data_q1; + adc_data_i2 <= adc_n_data_i2; + adc_data_q2 <= adc_n_data_q2; + adc_status <= adc_n_status; + end + // transmit data path mux (reverse of what receive does above) // the count simply selets the data muxing on the ddr outputs @@ -399,6 +414,20 @@ module axi_ad9361_dev_if ( endcase end + // transfer data from a synchronous clock (skew less than 2ns) + + always @(negedge clk) begin + tx_n_frame <= tx_frame; + tx_n_data_p <= tx_data_p; + tx_n_data_n <= tx_data_n; + end + + always @(posedge l_clk) begin + tx_p_frame <= tx_n_frame; + tx_p_data_p <= tx_n_data_p; + tx_p_data_n <= tx_n_data_n; + end + // delay write interface, each delay element can be individually // addressed, and a delay value can be directly loaded (no inc/dec stuff) @@ -517,7 +546,7 @@ module axi_ad9361_dev_if ( .CE (1'b1), .R (1'b0), .S (1'b0), - .C (clk), + .C (l_clk), .D (rx_data_idelay_s[l_inst]), .Q1 (rx_data_p_s[l_inst]), .Q2 (rx_data_n_s[l_inst])); @@ -595,7 +624,7 @@ module axi_ad9361_dev_if ( .CE (1'b1), .R (1'b0), .S (1'b0), - .C (clk), + .C (l_clk), .D (rx_frame_idelay_s), .Q1 (rx_frame_p_s), .Q2 (rx_frame_n_s)); @@ -613,9 +642,9 @@ module axi_ad9361_dev_if ( .CE (1'b1), .R (1'b0), .S (1'b0), - .C (clk), - .D1 (tx_data_p[l_inst]), - .D2 (tx_data_n[l_inst]), + .C (l_clk), + .D1 (tx_p_data_p[l_inst]), + .D2 (tx_p_data_n[l_inst]), .Q (tx_data_oddr_s[l_inst])); OBUFDS i_tx_data_obuf ( @@ -636,9 +665,9 @@ module axi_ad9361_dev_if ( .CE (1'b1), .R (1'b0), .S (1'b0), - .C (clk), - .D1 (tx_frame), - .D2 (tx_frame), + .C (l_clk), + .D1 (tx_p_frame), + .D2 (tx_p_frame), .Q (tx_frame_oddr_s)); OBUFDS i_tx_frame_obuf ( @@ -656,7 +685,7 @@ module axi_ad9361_dev_if ( .CE (1'b1), .R (1'b0), .S (1'b0), - .C (clk), + .C (l_clk), .D1 (1'b0), .D2 (1'b1), .Q (tx_clk_oddr_s)); @@ -679,11 +708,11 @@ module axi_ad9361_dev_if ( .CLR (1'b0), .CE (1'b1), .I (clk_ibuf_s), - .O (clk)); + .O (l_clk)); end else begin BUFG i_clk_gbuf ( .I (clk_ibuf_s), - .O (clk)); + .O (l_clk)); end endgenerate diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index 8396858d3..c3947c724 100755 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -61,10 +61,6 @@ module axi_ad9361_rx ( adc_status, adc_r1_mode, - // receive master/slave - adc_start_in, - adc_start_out, - // delay interface delay_clk, @@ -130,10 +126,6 @@ module axi_ad9361_rx ( input adc_status; output adc_r1_mode; - // receive master/slave - input adc_start_in; - output adc_start_out; - // delay interface input delay_clk; @@ -197,7 +189,6 @@ module axi_ad9361_rx ( reg up_adc_status_or = 'd0; reg [31:0] up_rdata = 'd0; reg up_ack = 'd0; - reg adc_start_out; // internal clocks and resets @@ -248,24 +239,10 @@ module axi_ad9361_rx ( wire up_ack_3_s; wire [31:0] up_rdata_s; wire up_ack_s; - wire adc_start_cond; - wire adc_valid_cond; - - assign adc_start_cond = (PCORE_ID == 32'd0) ? adc_start_out : adc_start_in; - - always @(posedge adc_clk) begin - if(adc_rst == 1'b1) begin - adc_start_out <= 1'b0; - end else begin - adc_start_out <= 1'b1; - end - end - - assign adc_valid_cond = adc_valid & adc_start_cond; // monitor signals - assign adc_mon_valid = adc_valid_cond; + assign adc_mon_valid = adc_valid; assign adc_mon_data[11: 0] = adc_data_i1; assign adc_mon_data[23:12] = adc_data_q1; assign adc_mon_data[35:24] = adc_data_i2; @@ -274,7 +251,7 @@ module axi_ad9361_rx ( // debug signals assign adc_dbg_trigger[0] = adc_iqcor_valid_s; - assign adc_dbg_trigger[1] = adc_valid_cond; + assign adc_dbg_trigger[1] = adc_valid; assign adc_dbg_data[ 15: 0] = adc_iqcor_data_0_s; assign adc_dbg_data[ 31: 16] = adc_iqcor_data_1_s; @@ -288,7 +265,7 @@ module axi_ad9361_rx ( assign adc_dbg_data[ 91: 80] = adc_data_q1; assign adc_dbg_data[103: 92] = adc_data_i2; assign adc_dbg_data[115:104] = adc_data_q2; - assign adc_dbg_data[116:116] = adc_valid_cond; + assign adc_dbg_data[116:116] = adc_valid; // adc channels - dma interface @@ -551,7 +528,7 @@ module axi_ad9361_rx ( i_rx_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_valid (adc_valid_cond), + .adc_valid (adc_valid), .adc_pn_oos_pl (adc_pn_oos_i1), .adc_pn_err_pl (adc_pn_err_i1), .adc_data (adc_data_i1), @@ -587,7 +564,7 @@ module axi_ad9361_rx ( i_rx_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_valid (adc_valid_cond), + .adc_valid (adc_valid), .adc_pn_oos_pl (adc_pn_oos_q1), .adc_pn_err_pl (adc_pn_err_q1), .adc_data (adc_data_q1), @@ -623,7 +600,7 @@ module axi_ad9361_rx ( i_rx_channel_2 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_valid (adc_valid_cond), + .adc_valid (adc_valid), .adc_pn_oos_pl (adc_pn_oos_i2), .adc_pn_err_pl (adc_pn_err_i2), .adc_data (adc_data_i2), @@ -659,7 +636,7 @@ module axi_ad9361_rx ( i_rx_channel_3 ( .adc_clk (adc_clk), .adc_rst (adc_rst), - .adc_valid (adc_valid_cond), + .adc_valid (adc_valid), .adc_pn_oos_pl (adc_pn_oos_q2), .adc_pn_err_pl (adc_pn_err_q2), .adc_data (adc_data_q2), diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index 0be0330ca..b35898b81 100755 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -59,7 +59,8 @@ module axi_ad9361_tx ( dac_data_q2, dac_r1_mode, - // transmit master/slave + // master/slave + dac_enable_in, dac_enable_out, @@ -104,7 +105,8 @@ module axi_ad9361_tx ( output [11:0] dac_data_q2; output dac_r1_mode; - // transmit master/slave + // master/slave + input dac_enable_in; output dac_enable_out; @@ -173,6 +175,7 @@ module axi_ad9361_tx ( wire up_ack_s; // master/slave + assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in; always @(posedge dac_clk) begin diff --git a/library/common/ad_iobuf.v b/library/common/ad_iobuf.v new file mode 100644 index 000000000..b8f40a7de --- /dev/null +++ b/library/common/ad_iobuf.v @@ -0,0 +1,70 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_iobuf ( + + dt, + di, + do, + dio); + + parameter DATA_WIDTH = 1; + + input [(DATA_WIDTH-1):0] dt; + input [(DATA_WIDTH-1):0] di; + output [(DATA_WIDTH-1):0] do; + inout [(DATA_WIDTH-1):0] dio; + + genvar n; + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf + IOBUF i_iobuf ( + .I (di[n]), + .O (do[n]), + .T (dt[n]), + .IO (dio[n])); + end + endgenerate + +endmodule + +// *************************************************************************** +// ***************************************************************************