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adrv9361z7035: Update README

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Istvan Csomortani 2017-05-25 17:47:19 +03:00
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projects/adrv9361z7035/README.md
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# PicoZed SDR SOM (PZSDR2) # ADRV1CRR SDR SOM
This folder contains the PZSDR2 SOM projects for each of the carrier boards. This folder contains the ADRV1CRR SOM projects for each of the carrier boards.
## Board Design Files ## Board Design Files
| Directory/File | Description | | Directory/File | Description |
|----------------------|----------------------------------------| |-----------------------------|----------------------------------------|
| common/pzsdr2_bd.tcl | pzsdr2 SOM module board design file. | | common/adrv9361z7035_bd.tcl | ADRV1CRR SOM module board design file. |
| common/ccbrk_bd.tcl | carrier, break out board design file. | | common/ccbob_bd.tcl | carrier, break out board design file. |
| common/ccfmc_bd.tcl | carrier, fmc board design file. | | common/ccfmc_bd.tcl | carrier, fmc board design file. |
| common/ccpci_bd.tcl | carrier, pci-e board design file. | | common/ccpci_bd.tcl | carrier, pci-e board design file. |
| common/ccusb_bd.tcl | carrier, usb board design file. | | common/ccusb_bd.tcl | carrier, usb board design file. |
FMC & BRK carrier designs includes loopback daughtercards for connectivity testing. FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.
## Board Constraint Files ## Board Constraint Files
| Directory/File | Description | | Directory/File | Description |
|-------------------------------|-----------------------------------------------| |--------------------------------------|-----------------------------------------------|
| common/pzsdr2_constr.xdc | pzsdr2 SOM base constraints file. | | common/adrv9361z7035_constr.xdc | ADRV1CRR SOM base constraints file. |
| common/pzsdr2_constr_cmos.xdc | pzsdr2 SOM CMOS mode constraints file. | | common/adrv9361z7035_constr_cmos.xdc | ADRV1CRR SOM CMOS mode constraints file. |
| common/pzsdr2_constr_lvds.xdc | pzsdr2 SOM LVDS mode constraints file. | | common/adrv9361z7035_constr_lvds.xdc | ADRV1CRR SOM LVDS mode constraints file. |
| common/ccbrk_constr.xdc | carrier, break out board constraints file. | | common/ccbob_constr.xdc | carrier, break out board constraints file. |
| common/ccfmc_constr.xdc | carrier, fmc board constraints file. | | common/ccfmc_constr.xdc | carrier, fmc board constraints file. |
| common/ccpci_constr.xdc | carrier, pci-e board constraints file. | | common/ccpci_constr.xdc | carrier, pci-e board constraints file. |
| common/ccusb_constr.xdc | carrier, usb board constraints file. | | common/ccusb_constr.xdc | carrier, usb board constraints file. |
@ -30,19 +30,19 @@ FMC & BRK carrier designs includes loopback daughtercards for connectivity testi
## Building, Generating Bit Files ## Building, Generating Bit Files
[pzsdr2] cd ccbrk_cmos [adrv9361z7035] cd ccbob_cmos
[pzsdr2/ccbrk_cmos] make [adrv9361z7035/ccbob_cmos] make
The make in each carrier directory builds the corresponding project. The above example builds PZSDR2-CCBRK hardware bit files in CMOS mode. The make in each carrier directory builds the corresponding project. The above example builds ADRV1CRR-BOB hardware bit files in CMOS mode.
## Documentation ## Documentation
* [HDL Design User Guide] * [HDL Design User Guide]
* [IP User Guide] * [IP User Guide]
* [PZSDR2 Wiki page] * [ADRV1CRR Wiki page]
[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl [HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl
[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361 [IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361
[PZSDR2 Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr [ADRV1CRR Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr