adrv9361z7035: Update README
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# PicoZed SDR SOM (PZSDR2)
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# ADRV1CRR SDR SOM
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This folder contains the PZSDR2 SOM projects for each of the carrier boards.
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This folder contains the ADRV1CRR SOM projects for each of the carrier boards.
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## Board Design Files
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| Directory/File | Description |
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|----------------------|----------------------------------------|
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| common/pzsdr2_bd.tcl | pzsdr2 SOM module board design file. |
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| common/ccbrk_bd.tcl | carrier, break out board design file. |
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|-----------------------------|----------------------------------------|
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| common/adrv9361z7035_bd.tcl | ADRV1CRR SOM module board design file. |
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| common/ccbob_bd.tcl | carrier, break out board design file. |
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| common/ccfmc_bd.tcl | carrier, fmc board design file. |
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| common/ccpci_bd.tcl | carrier, pci-e board design file. |
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| common/ccusb_bd.tcl | carrier, usb board design file. |
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FMC & BRK carrier designs includes loopback daughtercards for connectivity testing.
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FMC & BOB carrier designs includes loopback daughtercards for connectivity testing.
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## Board Constraint Files
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| Directory/File | Description |
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|-------------------------------|-----------------------------------------------|
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| common/pzsdr2_constr.xdc | pzsdr2 SOM base constraints file. |
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| common/pzsdr2_constr_cmos.xdc | pzsdr2 SOM CMOS mode constraints file. |
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| common/pzsdr2_constr_lvds.xdc | pzsdr2 SOM LVDS mode constraints file. |
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| common/ccbrk_constr.xdc | carrier, break out board constraints file. |
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|--------------------------------------|-----------------------------------------------|
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| common/adrv9361z7035_constr.xdc | ADRV1CRR SOM base constraints file. |
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| common/adrv9361z7035_constr_cmos.xdc | ADRV1CRR SOM CMOS mode constraints file. |
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| common/adrv9361z7035_constr_lvds.xdc | ADRV1CRR SOM LVDS mode constraints file. |
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| common/ccbob_constr.xdc | carrier, break out board constraints file. |
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| common/ccfmc_constr.xdc | carrier, fmc board constraints file. |
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| common/ccpci_constr.xdc | carrier, pci-e board constraints file. |
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| common/ccusb_constr.xdc | carrier, usb board constraints file. |
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@ -30,19 +30,19 @@ FMC & BRK carrier designs includes loopback daughtercards for connectivity testi
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## Building, Generating Bit Files
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[pzsdr2] cd ccbrk_cmos
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[adrv9361z7035] cd ccbob_cmos
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[pzsdr2/ccbrk_cmos] make
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[adrv9361z7035/ccbob_cmos] make
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The make in each carrier directory builds the corresponding project. The above example builds PZSDR2-CCBRK hardware bit files in CMOS mode.
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The make in each carrier directory builds the corresponding project. The above example builds ADRV1CRR-BOB hardware bit files in CMOS mode.
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## Documentation
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* [HDL Design User Guide]
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* [IP User Guide]
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* [PZSDR2 Wiki page]
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* [ADRV1CRR Wiki page]
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[HDL Design User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl
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[IP User Guide]:http://wiki.analog.com/resources/fpga/docs/axi_ad9361
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[PZSDR2 Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr
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[ADRV1CRR Wiki page]:https://wiki.analog.com/resources/eval/user-guides/picozed_sdr
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