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axi_logic_analyzer: Add module cascade support 

The trigger signal that goes to the DMA(fifo_wr_sync) does not pass through
the variable fifo, for this reason, a 3 clock cycles delay is required, to
keep in sync the data with the trigger.
On the other hand, to be able to cascade the axi_logic_analyzer with
axi_adc_trigger, there should be small delays on the trigger path, for this
reason the trigger_out_adc was created.

Remove the extra delays on the trigger_i(external trigger pins).
main
AndreiGrozav 2019-03-08 14:50:23 +00:00 committed by AndreiGrozav
parent 30bdb67994
commit 3b02a2a6c1
3 changed files with 42 additions and 24 deletions
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10
library/axi_logic_analyzer/axi_logic_analyzer.v
View File

@ -52,7 +52,9 @@ module axi_logic_analyzer (
input dac_valid, input dac_valid,
output reg dac_read, output reg dac_read,
input trigger_in,
output trigger_out, output trigger_out,
output trigger_out_adc,
output [31:0] fifo_depth, output [31:0] fifo_depth,
// axi interface // axi interface
@ -84,7 +86,6 @@ module axi_logic_analyzer (
reg [15:0] data_m1 = 'd0; reg [15:0] data_m1 = 'd0;
reg [15:0] data_r = 'd0; reg [15:0] data_r = 'd0;
reg [ 1:0] trigger_m1 = 'd0; reg [ 1:0] trigger_m1 = 'd0;
reg [ 1:0] trigger_m2 = 'd0;
reg [31:0] downsampler_counter_la = 'd0; reg [31:0] downsampler_counter_la = 'd0;
reg [31:0] upsampler_counter_pg = 'd0; reg [31:0] upsampler_counter_pg = 'd0;
@ -131,7 +132,7 @@ module axi_logic_analyzer (
wire [17:0] fall_edge_enable; wire [17:0] fall_edge_enable;
wire [17:0] low_level_enable; wire [17:0] low_level_enable;
wire [17:0] high_level_enable; wire [17:0] high_level_enable;
wire trigger_logic; // 0-OR,1-AND,2-XOR,3-NOR,4-NAND,5-NXOR wire [ 6:0] trigger_logic; // 0-OR,1-AND
wire clock_select; wire clock_select;
wire [15:0] overwrite_enable; wire [15:0] overwrite_enable;
wire [15:0] overwrite_data; wire [15:0] overwrite_data;
@ -223,7 +224,6 @@ module axi_logic_analyzer (
if (sample_valid_la == 1'b1) begin if (sample_valid_la == 1'b1) begin
data_m1 <= data_i; data_m1 <= data_i;
trigger_m1 <= trigger_i; trigger_m1 <= trigger_i;
trigger_m2 <= trigger_m1;
end end
end end
@ -297,7 +297,8 @@ module axi_logic_analyzer (
.data (adc_data_m2), .data (adc_data_m2),
.data_valid(sample_valid_la), .data_valid(sample_valid_la),
.trigger (trigger_m2), .trigger_i (trigger_m1),
.trigger_in (trigger_in),
.edge_detect_enable (edge_detect_enable), .edge_detect_enable (edge_detect_enable),
.rise_edge_enable (rise_edge_enable), .rise_edge_enable (rise_edge_enable),
@ -305,6 +306,7 @@ module axi_logic_analyzer (
.low_level_enable (low_level_enable), .low_level_enable (low_level_enable),
.high_level_enable (high_level_enable), .high_level_enable (high_level_enable),
.trigger_logic (trigger_logic), .trigger_logic (trigger_logic),
.trigger_out_adc (trigger_out_adc),
.trigger_out (trigger_out_s)); .trigger_out (trigger_out_s));
axi_logic_analyzer_reg i_registers ( axi_logic_analyzer_reg i_registers (

16
library/axi_logic_analyzer/axi_logic_analyzer_reg.v
View File

@ -51,7 +51,7 @@ module axi_logic_analyzer_reg (
output [17:0] high_level_enable, output [17:0] high_level_enable,
output [31:0] fifo_depth, output [31:0] fifo_depth,
output [31:0] trigger_delay, output [31:0] trigger_delay,
output trigger_logic, output [ 6:0] trigger_logic,
output clock_select, output clock_select,
output [15:0] overwrite_enable, output [15:0] overwrite_enable,
output [15:0] overwrite_data, output [15:0] overwrite_data,
@ -77,7 +77,7 @@ module axi_logic_analyzer_reg (
// internal registers // internal registers
reg [31:0] up_version = 32'h00010000; reg [31:0] up_version = 32'h00020100;
reg [31:0] up_scratch = 0; reg [31:0] up_scratch = 0;
reg [31:0] up_divider_counter_la = 0; reg [31:0] up_divider_counter_la = 0;
reg [31:0] up_divider_counter_pg = 0; reg [31:0] up_divider_counter_pg = 0;
@ -90,7 +90,7 @@ module axi_logic_analyzer_reg (
reg [17:0] up_high_level_enable = 0; reg [17:0] up_high_level_enable = 0;
reg [31:0] up_fifo_depth = 0; reg [31:0] up_fifo_depth = 0;
reg [31:0] up_trigger_delay = 0; reg [31:0] up_trigger_delay = 0;
reg up_trigger_logic = 0; reg [ 6:0] up_trigger_logic = 0;
reg up_clock_select = 0; reg up_clock_select = 0;
reg [15:0] up_overwrite_enable = 0; reg [15:0] up_overwrite_enable = 0;
reg [15:0] up_overwrite_data = 0; reg [15:0] up_overwrite_data = 0;
@ -154,7 +154,7 @@ module axi_logic_analyzer_reg (
up_fifo_depth <= up_wdata; up_fifo_depth <= up_wdata;
end end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
up_trigger_logic <= up_wdata[0]; up_trigger_logic <= up_wdata[6:0];
end end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
up_clock_select <= up_wdata[0]; up_clock_select <= up_wdata[0];
@ -203,7 +203,7 @@ module axi_logic_analyzer_reg (
5'h8: up_rdata <= {14'h0,up_low_level_enable}; 5'h8: up_rdata <= {14'h0,up_low_level_enable};
5'h9: up_rdata <= {14'h0,up_high_level_enable}; 5'h9: up_rdata <= {14'h0,up_high_level_enable};
5'ha: up_rdata <= up_fifo_depth; 5'ha: up_rdata <= up_fifo_depth;
5'hb: up_rdata <= {31'h0,up_trigger_logic}; 5'hb: up_rdata <= {25'h0,up_trigger_logic};
5'hc: up_rdata <= {31'h0,up_clock_select}; 5'hc: up_rdata <= {31'h0,up_clock_select};
5'hd: up_rdata <= {16'h0,up_overwrite_enable}; 5'hd: up_rdata <= {16'h0,up_overwrite_enable};
5'he: up_rdata <= {16'h0,up_overwrite_data}; 5'he: up_rdata <= {16'h0,up_overwrite_data};
@ -222,7 +222,7 @@ module axi_logic_analyzer_reg (
ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset)); ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
up_xfer_cntrl #(.DATA_WIDTH(285)) i_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(291)) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_streaming, // 1 .up_data_cntrl ({ up_streaming, // 1
@ -230,7 +230,7 @@ module axi_logic_analyzer_reg (
up_overwrite_data, // 16 up_overwrite_data, // 16
up_overwrite_enable, // 16 up_overwrite_enable, // 16
up_clock_select, // 1 up_clock_select, // 1
up_trigger_logic, // 1 up_trigger_logic, // 7
up_fifo_depth, // 32 up_fifo_depth, // 32
up_trigger_delay, // 32 up_trigger_delay, // 32
up_high_level_enable, // 18 up_high_level_enable, // 18
@ -250,7 +250,7 @@ module axi_logic_analyzer_reg (
overwrite_data, // 16 overwrite_data, // 16
overwrite_enable, // 16 overwrite_enable, // 16
clock_select, // 1 clock_select, // 1
trigger_logic, // 1 trigger_logic, // 7
fifo_depth, // 32 fifo_depth, // 32
trigger_delay, // 32 trigger_delay, // 32
high_level_enable, // 18 high_level_enable, // 18

40
library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
View File

@ -42,7 +42,8 @@ module axi_logic_analyzer_trigger (
input [15:0] data, input [15:0] data,
input data_valid, input data_valid,
input [ 1:0] trigger, input [ 1:0] trigger_i,
input trigger_in,
input [17:0] edge_detect_enable, input [17:0] edge_detect_enable,
input [17:0] rise_edge_enable, input [17:0] rise_edge_enable,
@ -50,9 +51,10 @@ module axi_logic_analyzer_trigger (
input [17:0] low_level_enable, input [17:0] low_level_enable,
input [17:0] high_level_enable, input [17:0] high_level_enable,
input trigger_logic, input [ 6:0] trigger_logic,
output reg trigger_out); output reg trigger_out,
output reg trigger_out_adc);
reg [ 17:0] data_m1 = 'd0; reg [ 17:0] data_m1 = 'd0;
reg [ 17:0] low_level = 'd0; reg [ 17:0] low_level = 'd0;
@ -60,26 +62,28 @@ module axi_logic_analyzer_trigger (
reg [ 17:0] edge_detect = 'd0; reg [ 17:0] edge_detect = 'd0;
reg [ 17:0] rise_edge = 'd0; reg [ 17:0] rise_edge = 'd0;
reg [ 17:0] fall_edge = 'd0; reg [ 17:0] fall_edge = 'd0;
reg [ 31:0] delay_count = 'd0;
reg trigger_active; reg trigger_active;
reg trigger_active_mux;
reg trigger_active_d1; reg trigger_active_d1;
reg trigger_active_d2; reg trigger_active_d2;
always @(posedge clk) begin always @(posedge clk) begin
if (data_valid == 1'b1) begin if (data_valid == 1'b1) begin
trigger_active_d1 <= trigger_active; trigger_active_d1 <= trigger_active_mux;
trigger_active_d2 <= trigger_active_d1; trigger_active_d2 <= trigger_active_d1;
trigger_out <= trigger_active_d2; trigger_out <= trigger_active_d2;
trigger_out_adc <= trigger_active_mux;
end end
end end
// trigger logic: // trigger logic:
// 0 OR // 0 OR
// 1 AND // 1 AND
always @(*) begin always @(*) begin
case (trigger_logic) case (trigger_logic[0])
0: trigger_active = |((edge_detect & edge_detect_enable) | 0: trigger_active = |((edge_detect & edge_detect_enable) |
(rise_edge & rise_edge_enable) | (rise_edge & rise_edge_enable) |
(fall_edge & fall_edge_enable) | (fall_edge & fall_edge_enable) |
@ -94,6 +98,18 @@ module axi_logic_analyzer_trigger (
endcase endcase
end end
always @(*) begin
case (trigger_logic[6:4])
3'd0: trigger_active_mux = trigger_active;
3'd1: trigger_active_mux = trigger_in;
3'd2: trigger_active_mux = trigger_active & trigger_in;
3'd3: trigger_active_mux = trigger_active | trigger_in;
3'd4: trigger_active_mux = trigger_active ^ trigger_in;
default: trigger_active_mux = 1'b1;
endcase
end
// internal signals // internal signals
always @(posedge clk) begin always @(posedge clk) begin
@ -106,12 +122,12 @@ module axi_logic_analyzer_trigger (
high_level <= 'd0; high_level <= 'd0;
end else begin end else begin
if (data_valid == 1'b1) begin if (data_valid == 1'b1) begin
data_m1 <= {trigger, data} ; data_m1 <= {trigger_i, data} ;
edge_detect <= data_m1 ^ {trigger, data}; edge_detect <= data_m1 ^ {trigger_i, data};
rise_edge <= (data_m1 ^ {trigger, data} ) & {trigger, data}; rise_edge <= (data_m1 ^ {trigger_i, data} ) & {trigger_i, data};
fall_edge <= (data_m1 ^ {trigger, data}) & ~{trigger, data}; fall_edge <= (data_m1 ^ {trigger_i, data}) & ~{trigger_i, data};
low_level <= ~{trigger, data}; low_level <= ~{trigger_i, data};
high_level <= {trigger, data}; high_level <= {trigger_i, data};
end end
end end
end end