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daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints

main
Adrian Costina 2015-04-30 12:14:03 +03:00
parent e332fa01c8
commit 3b58785368
2 changed files with 5 additions and 8 deletions
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8
projects/daq1/common/daq1_bd.tcl
View File

@ -47,7 +47,6 @@ set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] [get_bd_cells axi_ad9122_dm
set_property -dict [list CONFIG.PCORE_ID {1}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_CYCLIC {1}] [get_bd_cells axi_ad9122_dma]
@ -68,7 +67,6 @@ set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_dma
@ -144,7 +142,7 @@ ad_connect util_bsplit_rx_gt_data/data axi_daq1_gt/rx_gt_data
ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9250_jesd/gt1_rxdata
ad_connect axi_daq1_gt/rx_rst axi_ad9250_jesd/rx_reset
ad_connect axi_daq1_gt/rx_jesd_rst axi_ad9250_jesd/rx_reset
ad_connect axi_daq1_gt/rx_sysref axi_ad9250_jesd/rx_sysref
ad_connect axi_daq1_gt/rx_rst_done axi_ad9250_jesd/rx_reset_done
ad_connect axi_daq1_gt/rx_ip_comma_align axi_ad9250_jesd/rxencommaalign_out
@ -187,6 +185,10 @@ ad_connect dac_drd axi_ad9122_dma/fifo_rd_en
ad_connect dac_ddata axi_ad9122_dma/fifo_rd_dout
ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow
ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9250_dma/m_dest_axi_aresetn
# interconnect (cpu)
ad_cpu_interconnect 0x44A60000 axi_daq1_gt

5
projects/daq1/zc706/system_constr.xdc
View File

@ -74,9 +74,4 @@ create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_ad9122_dac_div_clk]
create_clock -name rx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_daq1_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {tx_div_clk}
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}