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library/axi_ad9361: mmcm rst for plls

main
Rejeesh Kutty 2016-05-04 13:39:26 -04:00
parent 16a13b2023
commit 3b5e44e37d
2 changed files with 15 additions and 11 deletions
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16
library/axi_ad9361/axi_ad9361.v
View File

@ -159,11 +159,7 @@ module axi_ad9361 (
up_dac_gpio_in,
up_dac_gpio_out,
up_adc_gpio_in,
up_adc_gpio_out,
// chipscope signals
tdd_dbg);
up_adc_gpio_out);
// parameters
@ -297,10 +293,6 @@ module axi_ad9361 (
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// chipscope signals
output [41:0] tdd_dbg;
// internal registers
reg up_wack = 'd0;
@ -315,6 +307,7 @@ module axi_ad9361 (
wire up_clk;
wire up_rstn;
wire mmcm_rst;
wire delay_rst;
// internal signals
@ -423,6 +416,7 @@ module axi_ad9361 (
.tdd_enable (tdd_enable_s),
.tdd_txnrx (tdd_txnrx_s),
.tdd_mode (tdd_mode_s),
.mmcm_rst (mmcm_rst),
.up_clk (up_clk),
.up_enable (up_enable),
.up_txnrx (up_txnrx),
@ -480,6 +474,7 @@ module axi_ad9361 (
.tdd_enable (tdd_enable_s),
.tdd_txnrx (tdd_txnrx_s),
.tdd_mode (tdd_mode_s),
.mmcm_rst (mmcm_rst),
.up_clk (up_clk),
.up_enable (up_enable),
.up_txnrx (up_txnrx),
@ -558,7 +553,7 @@ module axi_ad9361 (
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_tdd_s),
.up_rack (up_rack_tdd_s),
.tdd_dbg (tdd_dbg));
.tdd_dbg ());
// receive
@ -566,6 +561,7 @@ module axi_ad9361 (
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx (
.mmcm_rst (mmcm_rst),
.adc_rst (rst),
.adc_clk (clk),
.adc_valid (adc_valid_s),

10
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -40,6 +40,10 @@
module axi_ad9361_rx (
// common
mmcm_rst,
// adc interface
adc_rst,
@ -100,6 +104,10 @@ module axi_ad9361_rx (
parameter DATAPATH_DISABLE = 0;
parameter ID = 0;
// common
output mmcm_rst;
// adc interface
output adc_rst;
@ -335,7 +343,7 @@ module axi_ad9361_rx (
// common processor control
up_adc_common #(.ID (ID)) i_up_adc_common (
.mmcm_rst (),
.mmcm_rst (mmcm_rst),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (adc_r1_mode),