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axi_ad9963: Changed TX path from serdes to ddr. 

- remove delay control related logic
main
Adrian Costina 2017-03-30 21:12:58 +03:00 committed by Lars-Peter Clausen
parent 610cc3affa
commit 3c13aa49eb
5 changed files with 57 additions and 118 deletions
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18
library/axi_ad9963/axi_ad9963.v
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@ -44,7 +44,6 @@ module axi_ad9963 #(
parameter ID = 0, parameter ID = 0,
parameter DEVICE_TYPE = 0, parameter DEVICE_TYPE = 0,
parameter ADC_IODELAY_ENABLE = 0, parameter ADC_IODELAY_ENABLE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter DAC_DATAPATH_DISABLE = 0, parameter DAC_DATAPATH_DISABLE = 0,
parameter ADC_DATAPATH_DISABLE = 0 ) ( parameter ADC_DATAPATH_DISABLE = 0 ) (
@ -140,10 +139,6 @@ module axi_ad9963 #(
wire adc_status_s; wire adc_status_s;
wire dac_valid_s; wire dac_valid_s;
wire [23:0] dac_data_s; wire [23:0] dac_data_s;
wire dac_valid_i0_s;
wire dac_valid_q0_s;
wire dac_valid_i1_s;
wire dac_valid_q1_s;
wire [12:0] up_adc_dld_s; wire [12:0] up_adc_dld_s;
wire [64:0] up_adc_dwdata_s; wire [64:0] up_adc_dwdata_s;
wire [64:0] up_adc_drdata_s; wire [64:0] up_adc_drdata_s;
@ -168,9 +163,9 @@ module axi_ad9963 #(
// processor read interface // processor read interface
always @(*) begin always @(*) begin
up_wack <= up_wack_rx_s | up_wack_tx_s; up_wack = up_wack_rx_s | up_wack_tx_s;
up_rack <= up_rack_rx_s | up_rack_tx_s; up_rack = up_rack_rx_s | up_rack_tx_s;
up_rdata <= up_rdata_rx_s | up_rdata_tx_s; up_rdata = up_rdata_rx_s | up_rdata_tx_s;
end end
// device interface // device interface
@ -178,7 +173,6 @@ module axi_ad9963 #(
axi_ad9963_if #( axi_ad9963_if #(
.DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE), .ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
.IO_DELAY_GROUP (IO_DELAY_GROUP)) .IO_DELAY_GROUP (IO_DELAY_GROUP))
i_dev_if ( i_dev_if (
.trx_clk (trx_clk), .trx_clk (trx_clk),
@ -252,12 +246,6 @@ module axi_ad9963 #(
.dac_valid (dac_valid_s), .dac_valid (dac_valid_s),
.dac_data (dac_data_s), .dac_data (dac_data_s),
.adc_data (adc_data_s), .adc_data (adc_data_s),
.up_dld (),
.up_dwdata (),
.up_drdata (69'h0),
.delay_clk (delay_clk),
.delay_rst (),
.delay_locked (delay_locked_s),
.dac_sync_in (dac_sync_in), .dac_sync_in (dac_sync_in),
.dac_sync_out (dac_sync_out), .dac_sync_out (dac_sync_out),
.dac_enable_i (dac_enable_i), .dac_enable_i (dac_enable_i),

81
library/axi_ad9963/axi_ad9963_if.v
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@ -35,7 +35,6 @@ module axi_ad9963_if #(
// this parameter controls the buffer type based on the target device. // this parameter controls the buffer type based on the target device.
parameter DEVICE_TYPE = 0, parameter DEVICE_TYPE = 0,
parameter DAC_IODELAY_ENABLE = 0,
parameter ADC_IODELAY_ENABLE = 0, parameter ADC_IODELAY_ENABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") ( parameter IO_DELAY_GROUP = "dev_if_delay_group") (
@ -92,7 +91,6 @@ module axi_ad9963_if #(
wire rx_iq_p_s; wire rx_iq_p_s;
wire rx_iq_n_s; wire rx_iq_n_s;
wire tx_clk_serdes;
wire div_clk; wire div_clk;
genvar l_inst; genvar l_inst;
@ -179,56 +177,45 @@ module axi_ad9963_if #(
// transmit data interface // transmit data interface
BUFR #(.BUFR_DIVIDE(2)) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (tx_clk),
.O (div_clk));
BUFG dac_bufg ( BUFG dac_bufg (
.I(div_clk), .I(div_clk),
.O(dac_clk)); .O(dac_clk));
ad_serdes_clk #( generate
.DEVICE_TYPE(DEVICE_TYPE), for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
.DDR_OR_SDR_N(0), ODDR #(
.MMCM_OR_BUFR_N (1'b0), .DDR_CLK_EDGE ("SAME_EDGE"),
.CLKIN_DS_OR_SE_N(0), .INIT (1'b0),
.SERDES_FACTOR(2)) .SRTYPE ("SYNC"))
tx_serdes_clk ( i_tx_data_oddr (
.rst(1'b0), .CE (1'b1),
.clk_in_p(tx_clk), .R (dac_rst),
.clk_in_n(1'b0), .S (1'b0),
.clk(tx_clk_serdes), .C (dac_clk),
.div_clk(div_clk), .D1 (tx_data_p[l_inst]),
.out_clk(), .D2 (tx_data_n[l_inst]),
.loaden(), .Q (tx_data[l_inst]));
.phase(), end
.up_clk(1'b0), endgenerate
.up_rstn(1'b0),
.up_drp_sel(1'b0),
.up_drp_wr(1'b0),
.up_drp_addr(12'h0),
.up_drp_wdata(32'h0),
.up_drp_rdata(),
.up_drp_ready(),
.up_drp_locked());
ad_serdes_out #( ODDR #(
.DEVICE_TYPE (DEVICE_TYPE), .DDR_CLK_EDGE ("SAME_EDGE"),
.DDR_OR_SDR_N (1'b0), .INIT (1'b0),
.SERDES_FACTOR(2), .SRTYPE ("SYNC"))
.DATA_WIDTH (13)) i_tx_data_oddr (
i_serdes_out_data ( .CE (1'b1),
.rst (dac_rst), .R (dac_rst),
.clk (tx_clk_serdes), .S (1'b0),
.div_clk (div_clk), .C (dac_clk),
.loaden (1'b0), .D1 (1'b1),
.data_s0 ({1'b1,tx_data_p}), .D2 (1'b0),
.data_s1 ({1'b0,tx_data_n}), .Q (tx_iq));
.data_s2 (13'h0),
.data_s3 (13'h0),
.data_s4 (13'h0),
.data_s5 (13'h0),
.data_s6 (13'h0),
.data_s7 (13'h0),
.data_out_se ({tx_iq,tx_data}),
.data_out_p (),
.data_out_n ());
endmodule endmodule

2
library/axi_ad9963/axi_ad9963_ip.tcl
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@ -11,8 +11,6 @@ adi_ip_files axi_ad9963 [list \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \

41
library/axi_ad9963/axi_ad9963_tx.v
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@ -52,15 +52,6 @@ module axi_ad9963_tx #(
output [23:0] dac_data, output [23:0] dac_data,
input [23:0] adc_data, input [23:0] adc_data,
// delay interface
output [13:0] up_dld,
output [69:0] up_dwdata,
input [69:0] up_drdata,
input delay_clk,
output delay_rst,
input delay_locked,
// master/slave // master/slave
input dac_sync_in, input dac_sync_in,
@ -101,9 +92,9 @@ module axi_ad9963_tx #(
wire dac_dds_format_s; wire dac_dds_format_s;
wire [ 7:0] dac_datarate_s; wire [ 7:0] dac_datarate_s;
wire [23:0] dac_data_int_s; wire [23:0] dac_data_int_s;
wire [31:0] up_rdata_s[0:3]; wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:3]; wire up_rack_s[0:2];
wire up_wack_s[0:3]; wire up_wack_s[0:2];
// master/slave // master/slave
@ -134,9 +125,9 @@ module axi_ad9963_tx #(
// processor read interface // processor read interface
always @(*) begin always @(*) begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end end
// dac channel // dac channel
@ -242,26 +233,6 @@ module axi_ad9963_tx #(
.up_rdata (up_rdata_s[2]), .up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2])); .up_rack (up_rack_s[2]));
// dac delay control
up_delay_cntrl #(.DATA_WIDTH(14), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked),
.up_dld (up_dld),
.up_dwdata (up_dwdata),
.up_drdata (up_drdata),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
endmodule endmodule
// *************************************************************************** // ***************************************************************************

33
library/axi_ad9963/axi_ad9963_tx_channel.v
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@ -87,8 +87,6 @@ module axi_ad9963_tx_channel #(
reg dac_valid_sel = 'd0; reg dac_valid_sel = 'd0;
reg [23:0] dac_test_data = 'd0; reg [23:0] dac_test_data = 'd0;
reg [15:0] dac_test_counter = 'd0; reg [15:0] dac_test_counter = 'd0;
reg [23:0] dac_pn_seq = 'd0;
reg [11:0] dac_pn_data = 'd0;
reg [15:0] dac_pat_data = 'd0; reg [15:0] dac_pat_data = 'd0;
reg [15:0] dac_dds_phase_0 = 'd0; reg [15:0] dac_dds_phase_0 = 'd0;
reg [15:0] dac_dds_phase_1 = 'd0; reg [15:0] dac_dds_phase_1 = 'd0;
@ -114,16 +112,6 @@ module axi_ad9963_tx_channel #(
wire [15:0] dac_iqcor_coeff_1_s; wire [15:0] dac_iqcor_coeff_1_s;
wire [15:0] dac_iqcor_coeff_2_s; wire [15:0] dac_iqcor_coeff_2_s;
// global toggle
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_valid_sel <= 1'b0;
end else if (dac_valid == 1'b1) begin
dac_valid_sel <= ~dac_valid_sel;
end
end
// dac iq correction // dac iq correction
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
@ -186,7 +174,21 @@ module axi_ad9963_tx_channel #(
end end
end end
// dds
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_s = 16'd0;
end else begin
// pattern // pattern
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_valid_sel <= 1'b0;
end else if (dac_valid == 1'b1) begin
dac_valid_sel <= ~dac_valid_sel;
end
end
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if (dac_valid == 1'b1) begin if (dac_valid == 1'b1) begin
@ -198,13 +200,6 @@ module axi_ad9963_tx_channel #(
end end
end end
// dds
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_s = 16'd0;
end else begin
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin if (dac_data_sync == 1'b1) begin
dac_dds_phase_0 <= dac_dds_init_1_s; dac_dds_phase_0 <= dac_dds_init_1_s;