From 3c8369475590b2294ae8e009149a52164073576a Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 14 Nov 2019 16:24:53 +0200 Subject: [PATCH] adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock --- projects/common/xilinx/adi_fir_filter_bd.tcl | 27 +++++++++++++++---- .../common/xilinx/adi_fir_filter_constr.xdc | 7 +++++ 2 files changed, 29 insertions(+), 5 deletions(-) create mode 100644 projects/common/xilinx/adi_fir_filter_constr.xdc diff --git a/projects/common/xilinx/adi_fir_filter_bd.tcl b/projects/common/xilinx/adi_fir_filter_bd.tcl index 58bc0f2dd..dbce5418a 100644 --- a/projects/common/xilinx/adi_fir_filter_bd.tcl +++ b/projects/common/xilinx/adi_fir_filter_bd.tcl @@ -20,9 +20,17 @@ proc ad_add_decimation_filter {name filter_rate n_chan parallel_paths \ create_bd_pin -dir I $name/aclk create_bd_pin -dir I $name/active - # Adding the ad_bus_axis.v file in the project fileset sources_1 will not work - add_files -norecurse $ad_hdl_dir/library/common/ad_bus_mux.v + # Adding the ad_bus_axis.v file in the project fileset sources_1 will not work + add_files -norecurse $ad_hdl_dir/library/common/ad_bus_mux.v + add_files -norecurse $ad_hdl_dir/library/util_cdc/sync_bits.v + add_files -norecurse -fileset constrs_1 $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_constr.xdc + # cdc active/source + create_bd_cell -type module -reference sync_bits $name/cdc_sync_active + + ad_connect $name/aclk $name/cdc_sync_active/out_clk + ad_connect $name/cdc_sync_active/out_resetn VCC + ad_connect $name/active $name/cdc_sync_active/in_bits # add filter instances for n channels for {set i 0} {$i < $n_chan} {incr i} { @@ -79,7 +87,7 @@ proc ad_add_decimation_filter {name filter_rate n_chan parallel_paths \ ad_connect $name/enable_out_$i $name/out_mux_${i}/enable_out ad_connect $name/data_out_$i $name/out_mux_${i}/data_out - ad_connect $name/out_mux_${i}/select_path $name/active + ad_connect $name/cdc_sync_active/out_bits $name/out_mux_${i}/select_path } } @@ -104,10 +112,19 @@ proc ad_add_interpolation_filter {name filter_rate n_chan parallel_paths \ add_files -norecurse $ad_hdl_dir/library/common/ad_bus_mux.v add_files -norecurse $ad_hdl_dir/library/common/util_pulse_gen.v + add_files -norecurse $ad_hdl_dir/library/util_cdc/sync_bits.v + add_files -norecurse -fileset constrs_1 $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_constr.xdc create_bd_pin -dir I $name/aclk create_bd_pin -dir I $name/active + # cdc active/source + create_bd_cell -type module -reference sync_bits $name/cdc_sync_active + + ad_connect $name/aclk $name/cdc_sync_active/out_clk + ad_connect $name/cdc_sync_active/out_resetn VCC + ad_connect $name/active $name/cdc_sync_active/in_bits + # Create pulse generator for ready/valid signals - This is required because # there is only one clock domain for the slave and master data paths. # The generator will give a 1 clock cycle pulse every N clock cycle periods. @@ -121,7 +138,7 @@ proc ad_add_interpolation_filter {name filter_rate n_chan parallel_paths \ ad_connect $name/rate_gen/pulse_width GND ad_connect $name/rate_gen/pulse_period GND ad_connect $name/rate_gen/load_config GND - ad_connect $name/active $name/rate_gen/rstn + ad_connect $name/cdc_sync_active/out_bits $name/rate_gen/rstn # add filter instances for n channels for {set i 0} {$i < $n_chan} {incr i} { @@ -183,7 +200,7 @@ proc ad_add_interpolation_filter {name filter_rate n_chan parallel_paths \ ad_connect $name/out_mux_${i}/enable_out $name/enable_out_$i ad_connect $name/out_mux_${i}/data_out $name/data_out_$i - ad_connect $name/active $name/out_mux_${i}/select_path + ad_connect $name/cdc_sync_active/out_bits $name/out_mux_${i}/select_path } } diff --git a/projects/common/xilinx/adi_fir_filter_constr.xdc b/projects/common/xilinx/adi_fir_filter_constr.xdc new file mode 100644 index 000000000..3cbd84d44 --- /dev/null +++ b/projects/common/xilinx/adi_fir_filter_constr.xdc @@ -0,0 +1,7 @@ +# constraints + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ */cdc_sync_active/inst/cdc_sync_stage1_reg*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ */cdc_sync_active/inst/cdc_sync_stage2_reg*}] + +set_false_path -to [get_cells -hierarchical -filter {name =~ */cdc_sync_active/inst/cdc_sync_stage1_reg** && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hierarchical -filter {name =~ */cdc_sync_active/inst/cdc_sync_stage2_reg** && IS_SEQUENTIAL}]