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base system modifications

main
Rejeesh Kutty 2015-07-23 15:23:10 -04:00
parent a1733238df
commit 3ccf1bef36
4 changed files with 237 additions and 2202 deletions
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2331
projects/fmcjesdadc1/a5gt/system_bd.qsys
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File diff suppressed because one or more lines are too long

8
projects/fmcjesdadc1/a5gt/system_constr.sdc
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@ -7,10 +7,8 @@ derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -exclusive \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|a5gt_base|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
set_false_path -from [get_registers *dev_sync_n*] -to [get_registers *rx_sync_m1*]
set_false_path -from [get_registers *rx_sysref*] -to [get_registers *sys_xcvr*sysref*]

11
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -5,13 +5,16 @@ source ../../scripts/adi_env.tcl
project_new fmcjesdadc1_a5gt -overwrite
source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
file copy -force $ad_hdl_dir/projects/common/a5gt/a5gt_system_bd.qsys .
file copy -force $ad_hdl_dir/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys .
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE ../common/sys_xcvr.v
set_global_assignment -name QSYS_FILE sys_xcvr_rstcntrl_rx_pll.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_core.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_rx_ip.qsys
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top
# reference clock

89
projects/fmcjesdadc1/a5gt/system_top.v
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@ -213,55 +213,54 @@ module system_top (
.dataout (eth_tx_clk_out));
system_bd i_system_bd (
.rx_data_rx_d (rx_data),
.a5gt_base_sys_ddr3_oct_rzqin (ddr3_rzq),
.a5gt_base_sys_ddr3_phy_mem_a (ddr3_a),
.a5gt_base_sys_ddr3_phy_mem_ba (ddr3_ba),
.a5gt_base_sys_ddr3_phy_mem_ck (ddr3_clk_p),
.a5gt_base_sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
.a5gt_base_sys_ddr3_phy_mem_cke (ddr3_cke),
.a5gt_base_sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
.a5gt_base_sys_ddr3_phy_mem_dm (ddr3_dm),
.a5gt_base_sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
.a5gt_base_sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
.a5gt_base_sys_ddr3_phy_mem_we_n (ddr3_we_n),
.a5gt_base_sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
.a5gt_base_sys_ddr3_phy_mem_dq (ddr3_dq),
.a5gt_base_sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.a5gt_base_sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.a5gt_base_sys_ddr3_phy_mem_odt (ddr3_odt),
.a5gt_base_sys_125m_clk_clk (sys_125m_clk),
.a5gt_base_sys_25m_clk_clk (sys_25m_clk),
.a5gt_base_sys_2m5_clk_clk (sys_2m5_clk),
.a5gt_base_sys_ethernet_mdio_mdc (eth_mdc),
.a5gt_base_sys_ethernet_mdio_mdio_in (eth_mdio_i),
.a5gt_base_sys_ethernet_mdio_mdio_out (eth_mdio_o),
.a5gt_base_sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.a5gt_base_sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.a5gt_base_sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.a5gt_base_sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.a5gt_base_sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.a5gt_base_sys_ethernet_rx_clk_clk (eth_rx_clk),
.a5gt_base_sys_ethernet_status_set_10 (),
.a5gt_base_sys_ethernet_status_set_1000 (),
.a5gt_base_sys_ethernet_status_eth_mode (eth_tx_mode_1g),
.a5gt_base_sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
.a5gt_base_sys_ethernet_tx_clk_clk (eth_tx_clk),
.a5gt_base_sys_gpio_in_port (gpio_i[63:32]),
.a5gt_base_sys_gpio_out_port (gpio_o[63:32]),
.a5gt_base_sys_gpio_bd_in_port (gpio_i[31:0]),
.a5gt_base_sys_gpio_bd_out_port (gpio_o[31:0]),
.a5gt_base_sys_pll_locked_export (sys_pll_locked),
.a5gt_base_sys_spi_MISO (spi_miso),
.a5gt_base_sys_spi_MOSI (spi_mosi),
.a5gt_base_sys_spi_SCLK (spi_clk),
.a5gt_base_sys_spi_SS_n (spi_csn),
.rx_data_rx_serial_data (rx_data),
.rx_ref_clk_clk (ref_clk),
.rx_sync_rx_sync (rx_sync),
.rx_sysref_rx_ext_sysref_out (rx_sysref),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_clk_clk (sys_clk),
.sys_ddr3_oct_rzqin (ddr3_rzq),
.sys_ddr3_phy_mem_a (ddr3_a),
.sys_ddr3_phy_mem_ba (ddr3_ba),
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
.sys_ddr3_phy_mem_cke (ddr3_cke),
.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
.sys_ddr3_phy_mem_dm (ddr3_dm),
.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
.sys_ddr3_phy_mem_we_n (ddr3_we_n),
.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
.sys_ddr3_phy_mem_dq (ddr3_dq),
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.sys_ddr3_phy_mem_odt (ddr3_odt),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_gpio_in_port (gpio_i[63:32]),
.sys_gpio_out_port (gpio_o[63:32]),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_pll_locked_export (sys_pll_locked),
.sys_reset_reset_n (sys_resetn),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.tx_ref_clk_clk (1'd0));
.sys_reset_reset_n (sys_resetn));
endmodule