fmcjesdadc1:a10: Move block design into feature branch
Move block design file into the fmcjesdadc1_a10 feature branch.main
Istvan Csomortani
parent
c794cbb49d
commit
3ce9f55c39
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# ad9250-xcvr
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add_instance ad9250_jesd204 adi_jesd204
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set_instance_parameter_value ad9250_jesd204 {ID} {0}
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set_instance_parameter_value ad9250_jesd204 {TX_OR_RX_N} {0}
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set_instance_parameter_value ad9250_jesd204 {LANE_RATE} {5000.0}
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set_instance_parameter_value ad9250_jesd204 {REFCLK_FREQUENCY} {250.0}
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set_instance_parameter_value ad9250_jesd204 {NUM_OF_LANES} {4}
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set_instance_parameter_value ad9250_jesd204 {SOFT_PCS} {false}
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add_connection sys_clk.clk ad9250_jesd204.sys_clk
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add_connection sys_clk.clk_reset ad9250_jesd204.sys_resetn
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add_interface rx_ref_clk clock sink
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set_interface_property rx_ref_clk EXPORT_OF ad9250_jesd204.ref_clk
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add_interface rx_serial_data conduit end
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set_interface_property rx_serial_data EXPORT_OF ad9250_jesd204.serial_data
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add_interface rx_sysref conduit end
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set_interface_property rx_sysref EXPORT_OF ad9250_jesd204.sysref
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add_interface rx_sync conduit end
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set_interface_property rx_sync EXPORT_OF ad9250_jesd204.sync
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add_interface rx_ip_sof conduit end
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set_interface_property rx_ip_sof EXPORT_OF ad9250_jesd204.link_sof
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add_interface rx_ip_data avalon_streaming source
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set_interface_property rx_ip_data EXPORT_OF ad9250_jesd204.link_data
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# ad9250
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add_instance axi_ad9250_core_0 axi_ad9250
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set_instance_parameter_value axi_ad9250_core_0 {ID} {0}
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add_connection ad9250_jesd204.link_clk axi_ad9250_core_0.if_rx_clk
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add_connection sys_clk.clk_reset axi_ad9250_core_0.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_core_0.s_axi_clock
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add_interface rx_ip_sof_0 conduit end
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set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9250_core_0.if_rx_sof
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add_interface rx_ip_data_0 avalon_streaming sink
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set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9250_core_0.if_rx_data
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add_instance axi_ad9250_core_1 axi_ad9250
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set_instance_parameter_value axi_ad9250_core_1 {ID} {1}
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add_connection ad9250_jesd204.link_clk axi_ad9250_core_1.if_rx_clk
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add_connection sys_clk.clk_reset axi_ad9250_core_1.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock
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add_interface rx_ip_sof_1 conduit end
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set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9250_core_1.if_rx_sof
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add_interface rx_ip_data_1 avalon_streaming sink
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set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9250_core_1.if_rx_data
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# ad9250-pack
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add_instance util_ad9250_cpack_0 util_cpack
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set_instance_parameter_value util_ad9250_cpack_0 {CHANNEL_DATA_WIDTH} {32}
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set_instance_parameter_value util_ad9250_cpack_0 {NUM_OF_CHANNELS} {2}
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add_connection sys_clk.clk_reset util_ad9250_cpack_0.if_adc_rst
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add_connection ad9250_jesd204.link_clk util_ad9250_cpack_0.if_adc_clk
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add_connection axi_ad9250_core_0.adc_ch_0 util_ad9250_cpack_0.adc_ch_0
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add_connection axi_ad9250_core_0.adc_ch_1 util_ad9250_cpack_0.adc_ch_1
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add_instance util_ad9250_cpack_1 util_cpack
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set_instance_parameter_value util_ad9250_cpack_1 {CHANNEL_DATA_WIDTH} {32}
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set_instance_parameter_value util_ad9250_cpack_1 {NUM_OF_CHANNELS} {2}
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add_connection sys_clk.clk_reset util_ad9250_cpack_1.if_adc_rst
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add_connection ad9250_jesd204.link_clk util_ad9250_cpack_1.if_adc_clk
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add_connection axi_ad9250_core_1.adc_ch_0 util_ad9250_cpack_1.adc_ch_0
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add_connection axi_ad9250_core_1.adc_ch_1 util_ad9250_cpack_1.adc_ch_1
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# ad9250-dma
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add_instance axi_ad9250_dma_0 axi_dmac
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set_instance_parameter_value axi_ad9250_dma_0 {ID} {0}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_SRC} {2}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9250_dma_0 {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_DEST} {64}
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set_instance_parameter_value axi_ad9250_dma_0 {CYCLIC} {0}
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set_instance_parameter_value axi_ad9250_dma_0 {DMA_2D_TRANSFER} {0}
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add_connection ad9250_jesd204.link_clk axi_ad9250_dma_0.if_fifo_wr_clk
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add_connection util_ad9250_cpack_0.if_adc_valid axi_ad9250_dma_0.if_fifo_wr_en
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add_connection util_ad9250_cpack_0.if_adc_sync axi_ad9250_dma_0.if_fifo_wr_sync
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add_connection util_ad9250_cpack_0.if_adc_data axi_ad9250_dma_0.if_fifo_wr_din
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add_connection axi_ad9250_dma_0.if_fifo_wr_overflow axi_ad9250_core_0.if_adc_dovf
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add_connection sys_clk.clk_reset axi_ad9250_dma_0.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_dma_0.s_axi_clock
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add_connection sys_dma_clk.clk_reset axi_ad9250_dma_0.m_dest_axi_reset
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add_connection sys_dma_clk.clk axi_ad9250_dma_0.m_dest_axi_clock
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add_instance axi_ad9250_dma_1 axi_dmac
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set_instance_parameter_value axi_ad9250_dma_1 {ID} {1}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_SRC} {2}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_ad9250_dma_1 {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_DEST} {64}
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set_instance_parameter_value axi_ad9250_dma_1 {CYCLIC} {0}
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set_instance_parameter_value axi_ad9250_dma_1 {DMA_2D_TRANSFER} {0}
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add_connection ad9250_jesd204.link_clk axi_ad9250_dma_1.if_fifo_wr_clk
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add_connection util_ad9250_cpack_1.if_adc_valid axi_ad9250_dma_1.if_fifo_wr_en
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add_connection util_ad9250_cpack_1.if_adc_sync axi_ad9250_dma_1.if_fifo_wr_sync
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add_connection util_ad9250_cpack_1.if_adc_data axi_ad9250_dma_1.if_fifo_wr_din
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add_connection axi_ad9250_dma_1.if_fifo_wr_overflow axi_ad9250_core_1.if_adc_dovf
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add_connection sys_clk.clk_reset axi_ad9250_dma_1.s_axi_reset
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add_connection sys_clk.clk axi_ad9250_dma_1.s_axi_clock
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add_connection sys_dma_clk.clk_reset axi_ad9250_dma_1.m_dest_axi_reset
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add_connection sys_dma_clk.clk axi_ad9250_dma_1.m_dest_axi_clock
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# core-clock
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add_instance rx_core_clk altera_clock_bridge
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add_connection ad9250_jesd204.link_clk rx_core_clk.in_clk
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add_interface rx_core_clk clock source
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set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk
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#
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# reconfig sharing
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for {set i 0} {$i < 4} {incr i} {
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add_instance avl_adxcfg_${i} avl_adxcfg
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add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk
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add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n
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add_connection avl_adxcfg_${i}.rcfg_m0 ad9250_jesd204.phy_reconfig_${i}
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}
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# addresses
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ad_cpu_interconnect 0x00030000 ad9250_jesd204.link_reconfig
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ad_cpu_interconnect 0x00034000 ad9250_jesd204.link_management
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ad_cpu_interconnect 0x00035000 ad9250_jesd204.link_pll_reconfig
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ad_cpu_interconnect 0x00038000 avl_adxcfg_0.rcfg_s0
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ad_cpu_interconnect 0x00039000 avl_adxcfg_1.rcfg_s0
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ad_cpu_interconnect 0x0003a000 avl_adxcfg_2.rcfg_s0
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ad_cpu_interconnect 0x0003b000 avl_adxcfg_3.rcfg_s0
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ad_cpu_interconnect 0x00040000 axi_ad9250_core_0.s_axi
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ad_cpu_interconnect 0x00050000 axi_ad9250_core_1.s_axi
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ad_cpu_interconnect 0x00060000 axi_ad9250_dma_0.s_axi
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ad_cpu_interconnect 0x00070000 axi_ad9250_dma_1.s_axi
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# dma interconnects
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ad_dma_interconnect axi_ad9250_dma_0.m_dest_axi
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ad_dma_interconnect axi_ad9250_dma_1.m_dest_axi
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# interrupts
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ad_cpu_interrupt 10 ad9250_jesd204.interrupt
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ad_cpu_interrupt 11 axi_ad9250_dma_0.interrupt_sender
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ad_cpu_interrupt 12 axi_ad9250_dma_1.interrupt_sender
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