ad9783_zcu102_dev: Initial commit
Iulia Moldovan
imoldovan
parent
08f029c757
commit
3d000ee6a8
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# dac interface
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create_bd_port -dir O dci_p
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create_bd_port -dir O dci_n
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create_bd_port -dir I dco1_p
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create_bd_port -dir I dco1_n
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create_bd_port -dir O -from 15 -to 0 data_p
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create_bd_port -dir O -from 15 -to 0 data_n
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# dac peripherals
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ad_ip_instance axi_ad9783 axi_ad9783
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ad_ip_instance axi_dmac axi_ad9783_dma
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ad_ip_parameter axi_ad9783_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_ad9783_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_ad9783_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_ad9783_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9783_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_ad9783_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad9783_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_ad9783_dma CONFIG.DMA_AXI_PROTOCOL_SRC 1
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# dac-path channel upack
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ad_ip_instance util_upack2 util_ad9783_dac_upack { \
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NUM_OF_CHANNELS 2 \
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SAMPLES_PER_CHANNEL 4 \
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SAMPLE_DATA_WIDTH 16 \
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}
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# connections (dac)
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ad_connect dci_p axi_ad9783/dac_clk_out_p
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ad_connect dci_n axi_ad9783/dac_clk_out_n
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ad_connect dco1_p axi_ad9783/dac_clk_in_p
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ad_connect dco1_n axi_ad9783/dac_clk_in_n
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ad_connect data_p axi_ad9783/dac_data_out_p
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ad_connect data_n axi_ad9783/dac_data_out_n
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ad_connect dac_div_clk axi_ad9783/dac_div_clk
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ad_connect axi_ad9783/dac_valid util_ad9783_dac_upack/fifo_rd_en
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ad_connect axi_ad9783/dac_div_clk util_ad9783_dac_upack/clk
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ad_connect axi_ad9783/dac_div_clk axi_ad9783_dma/m_axis_aclk
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ad_connect axi_ad9783/dac_rst util_ad9783_dac_upack/reset
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ad_connect axi_ad9783/dac_enable_0 util_ad9783_dac_upack/enable_0
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ad_connect axi_ad9783/dac_enable_1 util_ad9783_dac_upack/enable_1
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ad_connect axi_ad9783_dma/m_axis util_ad9783_dac_upack/s_axis
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ad_connect util_ad9783_dac_upack/fifo_rd_data_0 axi_ad9783/dac_ddata_0
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ad_connect util_ad9783_dac_upack/fifo_rd_data_1 axi_ad9783/dac_ddata_1
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ad_connect util_ad9783_dac_upack/fifo_rd_underflow axi_ad9783/dac_dunf
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# interconnect (cpu)
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ad_cpu_interconnect 0x74200000 axi_ad9783
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ad_cpu_interconnect 0x7c420000 axi_ad9783_dma
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# interconnect (mem/dac)
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi
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ad_connect $sys_dma_resetn axi_ad9783_dma/m_src_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-12 mb-12 axi_ad9783_dma/irq
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@ -0,0 +1,23 @@
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad9783_zcu102
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M_DEPS += ../common/ad9783_ebz_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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LIB_DEPS += axi_ad9783
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += sysid_rom
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include ../../scripts/project-xilinx.mk
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source ../common/ad9783_ebz_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file
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# constraints
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# ad9783
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# dac_clk_in_p
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set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports dco1_p] ; ## H04 FMC_HPC0_CLK0_M2C_P
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# dac_clk_in_n
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set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports dco1_n] ; ## H05 FMC_HPC0_CLK0_M2C_N
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# dac_clk_out_p
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set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS} [get_ports dci_p] ; ## G6 FMC_HPC0_LA00_CC_P
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# dac_clk_out_n
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set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS} [get_ports dci_n] ; ## G7 FMC_HPC0_LA00_CC_N
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set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVDS} [get_ports data_p[0]] ; ## H19 FMC_HPC0_LA15_P
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set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVDS} [get_ports data_n[0]] ; ## H20 FMC_HPC0_LA15_N
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set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports data_p[1]] ; ## C18 FMC_HPC0_LA14_P
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set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports data_n[1]] ; ## C19 FMC_HPC0_LA14_N
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set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVDS} [get_ports data_p[2]] ; ## G18 FMC_HPC0_LA16_P
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set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVDS} [get_ports data_n[2]] ; ## G19 FMC_HPC0_LA16_N
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set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS} [get_ports data_p[3]] ; ## D14 FMC_HPC0_LA09_P
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set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS} [get_ports data_n[3]] ; ## D15 FMC_HPC0_LA09_N
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set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVDS} [get_ports data_p[4]] ; ## D17 FMC_HPC0_LA13_P
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set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVDS} [get_ports data_n[4]] ; ## D18 FMC_HPC0_LA13_N
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set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVDS} [get_ports data_p[5]] ; ## H16 FMC_HPC0_LA11_P
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set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVDS} [get_ports data_n[5]] ; ## H17 FMC_HPC0_LA11_N
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set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVDS} [get_ports data_p[6]] ; ## G15 FMC_HPC0_LA12_P
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set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVDS} [get_ports data_n[6]] ; ## G16 FMC_HPC0_LA12_N
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set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS} [get_ports data_p[7]] ; ## D11 FMC_HPC0_LA05_P
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set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS} [get_ports data_n[7]] ; ## D12 FMC_HPC0_LA05_N
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set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVDS} [get_ports data_p[8]] ; ## C14 FMC_HPC0_LA10_P
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set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVDS} [get_ports data_n[8]] ; ## C15 FMC_HPC0_LA10_N
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set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS} [get_ports data_p[9]] ; ## H13 FMC_HPC0_LA07_P
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set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS} [get_ports data_n[9]] ; ## H14 FMC_HPC0_LA07_N
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set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports data_p[10]] ; ## G12 FMC_HPC0_LA08_P
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set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports data_n[10]] ; ## G13 FMC_HPC0_LA08_N
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set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS} [get_ports data_p[11]] ; ## C10 FMC_HPC0_LA06_P
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set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS} [get_ports data_n[11]] ; ## C11 FMC_HPC0_LA06_N
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set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS} [get_ports data_p[12]] ; ## G9 FMC_HPC0_LA03_P
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set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS} [get_ports data_n[12]] ; ## G10 FMC_HPC0_LA03_N
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set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS} [get_ports data_p[13]] ; ## H7 FMC_HPC0_LA02_P
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set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS} [get_ports data_n[13]] ; ## H8 FMC_HPC0_LA02_N
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set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS} [get_ports data_p[14]] ; ## H10 FMC_HPC0_LA04_P
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set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS} [get_ports data_n[14]] ; ## H11 FMC_HPC0_LA04_N
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set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS} [get_ports data_p[15]] ; ## G2 FMC_HPC0_CLK1_M2C_P
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set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS} [get_ports data_n[15]] ; ## G3 FMC_HPC0_CLK1_M2C_N
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set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports spi_clk] ; ## IO_L10N_AD2N_47
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set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports spi_dio] ; ## IO_L10P_AD2P_47
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set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports spi_do] ; ## IO_L9N_AD3N_47
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports spi_en] ; ## IO_L9P_AD3P_47
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# clocks
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create_clock -name dco_p -period 2.00 [get_ports dco1_p]
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project ad9783_zcu102
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adi_project_files ad9783_zcu102 [list \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
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adi_project_run ad9783_zcu102
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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// dci_p&n enter the chip
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output dci_p,
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output dci_n,
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// dco_p&n leave the chip
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input dco1_p,
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input dco1_n,
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output [15:0] data_p,
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output [15:0] data_n,
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output spi_clk,
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output spi_dio,
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input spi_do,
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output spi_en);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [ 2:0] spi_csb;
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// defaults
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assign gpio_bd_o = gpio_o[20:13];
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assign gpio_i[94:13] = gpio_o[94:13];
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assign gpio_i[12: 0] = gpio_bd_i;
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assign spi_en = spi_csb[0];
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// instantiations
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (),
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.spi0_csn (spi_csb),
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.spi0_miso (spi_do),
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.spi0_mosi (spi_dio),
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.spi0_sclk (spi_clk),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi (),
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.spi1_sclk (),
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.dco1_n (dco1_n),
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.dco1_p (dco1_p),
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.dci_n (dci_n),
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.dci_p (dci_p),
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.data_n (data_n),
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.data_p (data_p));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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