From 3d8e05ac170d16f9dadefe938ec5463d7cc31445 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 17 May 2017 14:04:23 +0200 Subject: [PATCH] up_clock_mon: Make counter width configurable The clock monitor reports the ratio of the clock frequencies of a known reference clock and a monitored unknown clock. The frequency ratio is reported in a 16.16 fixed-point format. This means that it is possible to detect clocks that are 65535 times faster than the reference clock. For a reference clock of 100 MHz that is 6.5 THz and even if the reference clock is running at only 1 MHz it is still 65 GHz, a clock rate much faster than what we'd ever expect in a FPGA. Add a configuration option to the clock monitor that allows to reduce the number of integer bits of ratio. This allows to reduce the utilization while still being able to cover all realistic clock frequencies. Signed-off-by: Lars-Peter Clausen --- library/common/up_clock_mon.v | 40 ++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/library/common/up_clock_mon.v b/library/common/up_clock_mon.v index d00c5065e..78ba1492b 100644 --- a/library/common/up_clock_mon.v +++ b/library/common/up_clock_mon.v @@ -23,35 +23,37 @@ `timescale 1ns/100ps -module up_clock_mon ( +module up_clock_mon #( + parameter TOTAL_WIDTH = 32 +) ( // processor interface - input up_rstn, - input up_clk, - output reg [31:0] up_d_count, + input up_rstn, + input up_clk, + output reg [TOTAL_WIDTH-1:0] up_d_count, // device interface - input d_rst, - input d_clk); + input d_rst, + input d_clk); // internal registers - reg [15:0] up_count = 'd1; - reg up_count_run = 'd0; - reg up_count_running_m1 = 'd0; - reg up_count_running_m2 = 'd0; - reg up_count_running_m3 = 'd0; - reg d_count_run_m1 = 'd0; - reg d_count_run_m2 = 'd0; - reg d_count_run_m3 = 'd0; - reg [32:0] d_count = 'd0; + reg [15:0] up_count = 'd1; + reg up_count_run = 'd0; + reg up_count_running_m1 = 'd0; + reg up_count_running_m2 = 'd0; + reg up_count_running_m3 = 'd0; + reg d_count_run_m1 = 'd0; + reg d_count_run_m2 = 'd0; + reg d_count_run_m3 = 'd0; + reg [TOTAL_WIDTH:0] d_count = 'd0; // internal signals - wire up_count_capture_s; - wire d_count_reset_s; + wire up_count_capture_s; + wire d_count_reset_s; // processor reference @@ -118,10 +120,10 @@ module up_clock_mon ( if (d_count_reset_s == 1'b1) begin d_count <= 'h00; end else if (d_count_run_m3 == 1'b1) begin - if (d_count[32] == 1'b0) begin + if (d_count[TOTAL_WIDTH] == 1'b0) begin d_count <= d_count + 1'b1; end else begin - d_count <= {33{1'b1}}; + d_count <= {TOTAL_WIDTH+1{1'b1}}; end end end