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pluto_ng: Initial commit

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AndreiGrozav 2021-11-16 17:18:49 +02:00 committed by AndreiGrozav
parent 7dae0858b0
commit 3da9d9fcb4
5 changed files with 1218 additions and 0 deletions
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projects/pluto_ng/Makefile Normal file
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####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := pluto_ng
M_DEPS += ../scripts/adi_pd.tcl
M_DEPS += ../common/xilinx/adi_fir_filter_constr.xdc
M_DEPS += ../common/xilinx/adi_fir_filter_bd.tcl
M_DEPS += ../../library/util_cdc/sync_bits.v
M_DEPS += ../../library/common/util_pulse_gen.v
M_DEPS += ../../library/common/ad_iobuf.v
M_DEPS += ../../library/common/ad_bus_mux.v
LIB_DEPS += axi_adrv9001
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
include ../scripts/project-xilinx.mk

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projects/pluto_ng/system_bd.tcl Normal file
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# create board design
source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
# default ports
create_bd_port -dir O spi0_csn
create_bd_port -dir O spi0_sclk
create_bd_port -dir O spi0_mosi
create_bd_port -dir I spi0_miso
create_bd_port -dir I -from 94 -to 0 gpio_i
create_bd_port -dir O -from 94 -to 0 gpio_o
create_bd_port -dir O -from 94 -to 0 gpio_t
# ps8
ad_ip_instance zynq_ultra_ps_e sys_ps8
ad_ip_parameter sys_ps8 CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18}
ad_ip_parameter sys_ps8 CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18}
ad_ip_parameter sys_ps8 CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18}
ad_ip_parameter sys_ps8 CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18}
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 250
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 500
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO}
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 18 .. 23}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 16 .. 17}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4}
ad_ip_parameter sys_ps8 CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 39 .. 51}
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0}
# some sets of parameters must be configured at the same tine to avoid tools issues
set_property -dict [list CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
CONFIG.PSU__DP__LANE_SEL {Single Lower} \
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SATA__LANE0__ENABLE {0} \
CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane0} \
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk2} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
] [get_bd_cells sys_ps8]
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P}
set_property -dict [list CONFIG.SUBPRESET1 {Custom} \
CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1066} \
CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
CONFIG.PSU__DDRC__PARITY_ENABLE {1} \
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
CONFIG.PSU__DDRC__T_FAW {35} \
CONFIG.PSU__DDRC__CWL {11} \
CONFIG.PSU__DDRC__CL {15} \
CONFIG.PSU__DDRC__ECC {Disabled} \
] [get_bd_cells sys_ps8]
ad_ip_parameter sys_ps8 CONFIG.PSU_MIO_71_PULLUPDOWN {pulldown}
ad_ip_parameter sys_ps8 CONFIG.PSU_MIO_72_PULLUPDOWN {pulldown}
ad_ip_parameter sys_ps8 CONFIG.PSU_MIO_73_PULLUPDOWN {pulldown}
ad_ip_parameter sys_ps8 CONFIG.PSU_MIO_74_PULLUPDOWN {pulldown}
ad_ip_parameter sys_ps8 CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0}
set_property -dict [list CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 32 .. 33} \
] [get_bd_cells sys_ps8]
ad_ip_parameter sys_ps8 CONFIG.PSU__SATA__REF_CLK_FREQ {125}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__DP__REF_CLK_FREQ 108
ad_ip_parameter sys_ps8 CONFIG.PSU__USB0_COHERENCY 1
# system reset/clock definitions
# processor system reset instances for all the three system clocks
ad_ip_instance proc_sys_reset sys_rstgen
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
ad_ip_instance proc_sys_reset sys_250m_rstgen
ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1
ad_ip_instance proc_sys_reset sys_500m_rstgen
ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps8/pl_clk0
ad_connect sys_250m_clk sys_ps8/pl_clk1
ad_connect sys_500m_clk sys_ps8/pl_clk2
ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_ps8/pl_resetn0 sys_250m_rstgen/ext_reset_in
ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk
ad_connect sys_ps8/pl_resetn0 sys_500m_rstgen/ext_reset_in
ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset
ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn
ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset
ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn
# generic system clocks&resets pointers
set sys_cpu_clk [get_bd_nets sys_cpu_clk]
set sys_dma_clk [get_bd_nets sys_250m_clk]
set sys_iodelay_clk [get_bd_nets sys_500m_clk]
set sys_cpu_reset [get_bd_nets sys_cpu_reset]
set sys_cpu_resetn [get_bd_nets sys_cpu_resetn]
set sys_dma_reset [get_bd_nets sys_250m_reset]
set sys_dma_resetn [get_bd_nets sys_250m_resetn]
set sys_iodelay_reset [get_bd_nets sys_500m_reset]
set sys_iodelay_resetn [get_bd_nets sys_500m_resetn]
# gpio
ad_connect gpio_i sys_ps8/emio_gpio_i
ad_connect gpio_o sys_ps8/emio_gpio_o
ad_connect gpio_t sys_ps8/emio_gpio_t
# spi
ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn
ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
ad_connect sys_ps8/emio_spi0_m_i spi0_miso
ad_connect sys_ps8/emio_spi0_ss_i_n VCC
ad_connect sys_ps8/emio_spi0_sclk_i GND
ad_connect sys_ps8/emio_spi0_s_i GND
#system ID
ad_ip_instance axi_sysid axi_sysid_0
ad_ip_instance sysid_rom rom_sys_0
ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr
ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data
ad_connect sys_cpu_clk rom_sys_0/clk
# interrupts
ad_ip_instance xlconcat sys_concat_intc_0
ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
ad_ip_instance xlconcat sys_concat_intc_1
ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
ad_connect sys_concat_intc_0/In7 GND
ad_connect sys_concat_intc_0/In6 GND
ad_connect sys_concat_intc_0/In5 GND
ad_connect sys_concat_intc_0/In4 GND
ad_connect sys_concat_intc_0/In3 GND
ad_connect sys_concat_intc_0/In2 GND
ad_connect sys_concat_intc_0/In1 GND
ad_connect sys_concat_intc_0/In0 GND
ad_connect sys_concat_intc_1/In7 GND
ad_connect sys_concat_intc_1/In6 GND
ad_connect sys_concat_intc_1/In5 GND
ad_connect sys_concat_intc_1/In4 GND
ad_connect sys_concat_intc_1/In3 GND
ad_connect sys_concat_intc_1/In2 GND
ad_connect sys_concat_intc_1/In1 GND
ad_connect sys_concat_intc_1/In0 GND
# adrv9001 interface
create_bd_port -dir I rx1_dclk_in_n
create_bd_port -dir I rx1_dclk_in_p
create_bd_port -dir I rx1_idata_in_n
create_bd_port -dir I rx1_idata_in_p
create_bd_port -dir I rx1_qdata_in_n
create_bd_port -dir I rx1_qdata_in_p
create_bd_port -dir I rx1_strobe_in_n
create_bd_port -dir I rx1_strobe_in_p
create_bd_port -dir I rx2_dclk_in_n
create_bd_port -dir I rx2_dclk_in_p
create_bd_port -dir I rx2_idata_in_n
create_bd_port -dir I rx2_idata_in_p
create_bd_port -dir I rx2_qdata_in_n
create_bd_port -dir I rx2_qdata_in_p
create_bd_port -dir I rx2_strobe_in_n
create_bd_port -dir I rx2_strobe_in_p
create_bd_port -dir O tx1_dclk_out_n
create_bd_port -dir O tx1_dclk_out_p
create_bd_port -dir I tx1_dclk_in_n
create_bd_port -dir I tx1_dclk_in_p
create_bd_port -dir O tx1_idata_out_n
create_bd_port -dir O tx1_idata_out_p
create_bd_port -dir O tx1_qdata_out_n
create_bd_port -dir O tx1_qdata_out_p
create_bd_port -dir O tx1_strobe_out_n
create_bd_port -dir O tx1_strobe_out_p
create_bd_port -dir O tx2_dclk_out_n
create_bd_port -dir O tx2_dclk_out_p
create_bd_port -dir I tx2_dclk_in_n
create_bd_port -dir I tx2_dclk_in_p
create_bd_port -dir O tx2_idata_out_n
create_bd_port -dir O tx2_idata_out_p
create_bd_port -dir O tx2_qdata_out_n
create_bd_port -dir O tx2_qdata_out_p
create_bd_port -dir O tx2_strobe_out_n
create_bd_port -dir O tx2_strobe_out_p
create_bd_port -dir O rx1_enable
create_bd_port -dir O rx2_enable
create_bd_port -dir O tx1_enable
create_bd_port -dir O tx2_enable
create_bd_port -dir I gpio_rx1_enable_in
create_bd_port -dir I gpio_rx2_enable_in
create_bd_port -dir I gpio_tx1_enable_in
create_bd_port -dir I gpio_tx2_enable_in
create_bd_port -dir I ref_clk
create_bd_port -dir I tx_output_enable
create_bd_port -dir I mssi_sync
create_bd_port -dir I system_sync
create_bd_port -dir I s_1p0_rf_sns_p
create_bd_port -dir I s_1p0_rf_sns_n
create_bd_port -dir I s_1p8_rf_sns_p
create_bd_port -dir I s_1p8_rf_sns_n
create_bd_port -dir I s_1p3_rf_sns_p
create_bd_port -dir I s_1p3_rf_sns_n
create_bd_port -dir I s_5v0_rf_sns_p
create_bd_port -dir I s_5v0_rf_sns_n
create_bd_port -dir I s_2v5_sns_p
create_bd_port -dir I s_2v5_sns_n
create_bd_port -dir I s_vtt_ps_ddr4_sns_p
create_bd_port -dir I s_vtt_ps_ddr4_sns_n
create_bd_port -dir I s_1v2_ps_ddr4_sns_p
create_bd_port -dir I s_1v2_ps_ddr4_sns_n
create_bd_port -dir I s_0v85_mgtravcc_sns_p
create_bd_port -dir I s_0v85_mgtravcc_sns_n
create_bd_port -dir I s_5v0_sns_p
create_bd_port -dir I s_5v0_sns_n
create_bd_port -dir I s_1v2_sns_p
create_bd_port -dir I s_1v2_sns_n
create_bd_port -dir I s_1v8_mgtravtt_sns_p
create_bd_port -dir I s_1v8_mgtravtt_sns_n
# adrv9001
ad_ip_instance axi_adrv9001 axi_adrv9001
ad_ip_parameter axi_adrv9001 CONFIG.CMOS_LVDS_N 0
ad_ip_parameter axi_adrv9001 CONFIG.USE_RX_CLK_FOR_TX 0
ad_ip_parameter axi_adrv9001 CONFIG.EXT_SYNC 1
# dma for rx1
ad_ip_instance axi_dmac axi_adrv9001_rx1_dma
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_instance util_cpack2 util_adc_1_pack { \
NUM_OF_CHANNELS 4 \
SAMPLE_DATA_WIDTH 16 \
}
# dma for rx2
ad_ip_instance axi_dmac axi_adrv9001_rx2_dma
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_instance util_cpack2 util_adc_2_pack { \
NUM_OF_CHANNELS 2 \
SAMPLE_DATA_WIDTH 16 \
}
# dma for tx1
ad_ip_instance axi_dmac axi_adrv9001_tx1_dma
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_upack2 util_dac_1_upack { \
NUM_OF_CHANNELS 4 \
SAMPLE_DATA_WIDTH 16 \
}
# dma for tx2
ad_ip_instance axi_dmac axi_adrv9001_tx2_dma
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_DATA_WIDTH_DEST 32
ad_ip_instance util_upack2 util_dac_2_upack { \
NUM_OF_CHANNELS 2 \
SAMPLE_DATA_WIDTH 16 \
}
# ad9001 connections
ad_connect $sys_iodelay_clk axi_adrv9001/delay_clk
ad_connect axi_adrv9001/adc_1_clk axi_adrv9001_rx1_dma/fifo_wr_clk
ad_connect axi_adrv9001/adc_1_clk util_adc_1_pack/clk
ad_connect axi_adrv9001/adc_2_clk axi_adrv9001_rx2_dma/fifo_wr_clk
ad_connect axi_adrv9001/adc_2_clk util_adc_2_pack/clk
ad_connect axi_adrv9001/dac_1_clk axi_adrv9001_tx1_dma/m_axis_aclk
ad_connect axi_adrv9001/dac_1_clk util_dac_1_upack/clk
ad_connect axi_adrv9001/dac_2_clk axi_adrv9001_tx2_dma/m_axis_aclk
ad_connect axi_adrv9001/dac_2_clk util_dac_2_upack/clk
ad_connect ref_clk axi_adrv9001/ref_clk
ad_connect tx_output_enable axi_adrv9001/tx_output_enable
ad_connect mssi_sync axi_adrv9001/mssi_sync
ad_connect rx1_dclk_in_n axi_adrv9001/rx1_dclk_in_n_NC
ad_connect rx1_dclk_in_p axi_adrv9001/rx1_dclk_in_p_dclk_in
ad_connect rx1_idata_in_n axi_adrv9001/rx1_idata_in_n_idata0
ad_connect rx1_idata_in_p axi_adrv9001/rx1_idata_in_p_idata1
ad_connect rx1_qdata_in_n axi_adrv9001/rx1_qdata_in_n_qdata2
ad_connect rx1_qdata_in_p axi_adrv9001/rx1_qdata_in_p_qdata3
ad_connect rx1_strobe_in_n axi_adrv9001/rx1_strobe_in_n_NC
ad_connect rx1_strobe_in_p axi_adrv9001/rx1_strobe_in_p_strobe_in
ad_connect rx2_dclk_in_n axi_adrv9001/rx2_dclk_in_n_NC
ad_connect rx2_dclk_in_p axi_adrv9001/rx2_dclk_in_p_dclk_in
ad_connect rx2_idata_in_n axi_adrv9001/rx2_idata_in_n_idata0
ad_connect rx2_idata_in_p axi_adrv9001/rx2_idata_in_p_idata1
ad_connect rx2_qdata_in_n axi_adrv9001/rx2_qdata_in_n_qdata2
ad_connect rx2_qdata_in_p axi_adrv9001/rx2_qdata_in_p_qdata3
ad_connect rx2_strobe_in_n axi_adrv9001/rx2_strobe_in_n_NC
ad_connect rx2_strobe_in_p axi_adrv9001/rx2_strobe_in_p_strobe_in
ad_connect tx1_dclk_out_n axi_adrv9001/tx1_dclk_out_n_NC
ad_connect tx1_dclk_out_p axi_adrv9001/tx1_dclk_out_p_dclk_out
ad_connect tx1_dclk_in_n axi_adrv9001/tx1_dclk_in_n_NC
ad_connect tx1_dclk_in_p axi_adrv9001/tx1_dclk_in_p_dclk_in
ad_connect tx1_idata_out_n axi_adrv9001/tx1_idata_out_n_idata0
ad_connect tx1_idata_out_p axi_adrv9001/tx1_idata_out_p_idata1
ad_connect tx1_qdata_out_n axi_adrv9001/tx1_qdata_out_n_qdata2
ad_connect tx1_qdata_out_p axi_adrv9001/tx1_qdata_out_p_qdata3
ad_connect tx1_strobe_out_n axi_adrv9001/tx1_strobe_out_n_NC
ad_connect tx1_strobe_out_p axi_adrv9001/tx1_strobe_out_p_strobe_out
ad_connect tx2_dclk_out_n axi_adrv9001/tx2_dclk_out_n_NC
ad_connect tx2_dclk_out_p axi_adrv9001/tx2_dclk_out_p_dclk_out
ad_connect tx2_dclk_in_n axi_adrv9001/tx2_dclk_in_n_NC
ad_connect tx2_dclk_in_p axi_adrv9001/tx2_dclk_in_p_dclk_in
ad_connect tx2_idata_out_n axi_adrv9001/tx2_idata_out_n_idata0
ad_connect tx2_idata_out_p axi_adrv9001/tx2_idata_out_p_idata1
ad_connect tx2_qdata_out_n axi_adrv9001/tx2_qdata_out_n_qdata2
ad_connect tx2_qdata_out_p axi_adrv9001/tx2_qdata_out_p_qdata3
ad_connect tx2_strobe_out_n axi_adrv9001/tx2_strobe_out_n_NC
ad_connect tx2_strobe_out_p axi_adrv9001/tx2_strobe_out_p_strobe_out
# RX1_RX2 - CPACK - RX_DMA1
ad_connect axi_adrv9001/adc_1_rst util_adc_1_pack/reset
ad_connect axi_adrv9001/adc_1_valid_i0 util_adc_1_pack/fifo_wr_en
ad_connect axi_adrv9001/adc_1_enable_i0 util_adc_1_pack/enable_0
ad_connect axi_adrv9001/adc_1_data_i0 util_adc_1_pack/fifo_wr_data_0
ad_connect axi_adrv9001/adc_1_enable_q0 util_adc_1_pack/enable_1
ad_connect axi_adrv9001/adc_1_data_q0 util_adc_1_pack/fifo_wr_data_1
ad_connect axi_adrv9001/adc_1_enable_i1 util_adc_1_pack/enable_2
ad_connect axi_adrv9001/adc_1_data_i1 util_adc_1_pack/fifo_wr_data_2
ad_connect axi_adrv9001/adc_1_enable_q1 util_adc_1_pack/enable_3
ad_connect axi_adrv9001/adc_1_data_q1 util_adc_1_pack/fifo_wr_data_3
ad_connect axi_adrv9001/adc_1_dovf util_adc_1_pack/fifo_wr_overflow
ad_connect util_adc_1_pack/packed_fifo_wr axi_adrv9001_rx1_dma/fifo_wr
# RX2 - CPACK - RX_DMA2
ad_connect axi_adrv9001/adc_2_rst util_adc_2_pack/reset
ad_connect axi_adrv9001/adc_2_valid_i0 util_adc_2_pack/fifo_wr_en
ad_connect axi_adrv9001/adc_2_enable_i0 util_adc_2_pack/enable_0
ad_connect axi_adrv9001/adc_2_data_i0 util_adc_2_pack/fifo_wr_data_0
ad_connect axi_adrv9001/adc_2_enable_q0 util_adc_2_pack/enable_1
ad_connect axi_adrv9001/adc_2_data_q0 util_adc_2_pack/fifo_wr_data_1
ad_connect axi_adrv9001/adc_2_dovf util_adc_2_pack/fifo_wr_overflow
ad_connect util_adc_2_pack/packed_fifo_wr axi_adrv9001_rx2_dma/fifo_wr
# TX_DMA1 - UPACK - TX1
ad_connect axi_adrv9001/dac_1_rst util_dac_1_upack/reset
ad_connect axi_adrv9001/dac_1_valid_i0 util_dac_1_upack/fifo_rd_en
ad_connect axi_adrv9001/dac_1_enable_i0 util_dac_1_upack/enable_0
ad_connect axi_adrv9001/dac_1_data_i0 util_dac_1_upack/fifo_rd_data_0
ad_connect axi_adrv9001/dac_1_enable_q0 util_dac_1_upack/enable_1
ad_connect axi_adrv9001/dac_1_data_q0 util_dac_1_upack/fifo_rd_data_1
ad_connect axi_adrv9001/dac_1_enable_i1 util_dac_1_upack/enable_2
ad_connect axi_adrv9001/dac_1_data_i1 util_dac_1_upack/fifo_rd_data_2
ad_connect axi_adrv9001/dac_1_enable_q1 util_dac_1_upack/enable_3
ad_connect axi_adrv9001/dac_1_data_q1 util_dac_1_upack/fifo_rd_data_3
ad_connect axi_adrv9001_tx1_dma/m_axis util_dac_1_upack/s_axis
ad_connect axi_adrv9001/dac_1_dunf util_dac_1_upack/fifo_rd_underflow
# TX_DMA2 - UPACK - TX2
ad_connect axi_adrv9001/dac_2_rst util_dac_2_upack/reset
ad_connect axi_adrv9001/dac_2_valid_i0 util_dac_2_upack/fifo_rd_en
ad_connect axi_adrv9001/dac_2_enable_i0 util_dac_2_upack/enable_0
ad_connect axi_adrv9001/dac_2_data_i0 util_dac_2_upack/fifo_rd_data_0
ad_connect axi_adrv9001/dac_2_enable_q0 util_dac_2_upack/enable_1
ad_connect axi_adrv9001/dac_2_data_q0 util_dac_2_upack/fifo_rd_data_1
ad_connect axi_adrv9001_tx2_dma/m_axis util_dac_2_upack/s_axis
ad_connect axi_adrv9001/dac_2_dunf util_dac_2_upack/fifo_rd_underflow
ad_connect gpio_rx1_enable_in axi_adrv9001/gpio_rx1_enable_in
ad_connect gpio_rx2_enable_in axi_adrv9001/gpio_rx2_enable_in
ad_connect gpio_tx1_enable_in axi_adrv9001/gpio_tx1_enable_in
ad_connect gpio_tx2_enable_in axi_adrv9001/gpio_tx2_enable_in
ad_connect rx1_enable axi_adrv9001/rx1_enable
ad_connect rx2_enable axi_adrv9001/rx2_enable
ad_connect tx1_enable axi_adrv9001/tx1_enable
ad_connect tx2_enable axi_adrv9001/tx2_enable
ad_connect system_sync axi_adrv9001/adc_sync_in
ad_connect system_sync axi_adrv9001/dac_sync_in
# sysytem monitor
ad_ip_instance system_management_wiz pl_sysmon
set_property -dict [list \
CONFIG.CHANNEL_ENABLE_VBRAM {true} \
CONFIG.CHANNEL_ENABLE_VP_VN {false} \
CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP2_VAUXN2 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP3_VAUXN3 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP4_VAUXN4 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP5_VAUXN5 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP7_VAUXN7 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP8_VAUXN8 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 {true} \
CONFIG.CHANNEL_ENABLE_VAUXP10_VAUXN10 {true} \
CONFIG.CHANNEL_ENABLE_VUSER0 {true} \
CONFIG.USER_SUPPLY0_ALARM {false} \
CONFIG.USER_SUPPLY0_BANK {66} \
CONFIG.ANALOG_BANK_SELECTION {66} \
CONFIG.VAUXN0_LOC {A8} \
CONFIG.VAUXP0_LOC {A9} \
CONFIG.VAUXN1_LOC {B8} \
CONFIG.VAUXP1_LOC {C8} \
CONFIG.VAUXN2_LOC {F7} \
CONFIG.VAUXP2_LOC {G7} \
CONFIG.VAUXN3_LOC {F8} \
CONFIG.VAUXP3_LOC {G8} \
CONFIG.VAUXN4_LOC {B2} \
CONFIG.VAUXP4_LOC {B3} \
CONFIG.VAUXN5_LOC {A2} \
CONFIG.VAUXP5_LOC {A3} \
CONFIG.VAUXN6_LOC {H3} \
CONFIG.VAUXP6_LOC {H4} \
CONFIG.VAUXN7_LOC {F3} \
CONFIG.VAUXP7_LOC {G3} \
CONFIG.VAUXN8_LOC {B5} \
CONFIG.VAUXP8_LOC {C5} \
CONFIG.VAUXN9_LOC {A5} \
CONFIG.VAUXP9_LOC {A6} \
CONFIG.VAUXN10_LOC {G6} \
CONFIG.VAUXP10_LOC {H6} \
CONFIG.UNDER_TEMP_ALARM {true} \
CONFIG.COMMON_N_SOURCE {Vaux6}] [get_bd_cells pl_sysmon]
ad_connect pl_sysmon/vauxp0 s_1v2_ps_ddr4_sns_p
ad_connect pl_sysmon/vauxn0 s_1v2_ps_ddr4_sns_n
ad_connect pl_sysmon/vauxp1 s_2v5_sns_p
ad_connect pl_sysmon/vauxn1 s_2v5_sns_n
ad_connect pl_sysmon/vauxp2 s_1p3_rf_sns_p
ad_connect pl_sysmon/vauxn2 s_1p3_rf_sns_n
ad_connect pl_sysmon/vauxp3 s_1p0_rf_sns_p
ad_connect pl_sysmon/vauxn3 s_1p0_rf_sns_n
ad_connect pl_sysmon/vauxp4 s_1v8_mgtravtt_sns_p
ad_connect pl_sysmon/vauxn4 s_1v8_mgtravtt_sns_n
ad_connect pl_sysmon/vauxp5 s_1v2_sns_p
ad_connect pl_sysmon/vauxn5 s_1v2_sns_n
ad_connect pl_sysmon/vauxp6 s_5v0_sns_p
ad_connect pl_sysmon/vauxn6 s_5v0_sns_n
ad_connect pl_sysmon/vauxp7 s_0v85_mgtravcc_sns_p
ad_connect pl_sysmon/vauxn7 s_0v85_mgtravcc_sns_n
ad_connect pl_sysmon/vauxp8 s_vtt_ps_ddr4_sns_p
ad_connect pl_sysmon/vauxn8 s_vtt_ps_ddr4_sns_n
ad_connect pl_sysmon/vauxp9 s_5v0_rf_sns_p
ad_connect pl_sysmon/vauxn9 s_5v0_rf_sns_n
ad_connect pl_sysmon/vauxp10 s_1p8_rf_sns_p
ad_connect pl_sysmon/vauxn10 s_1p8_rf_sns_n
ad_connect sys_cpu_clk pl_sysmon/s_axi_aclk
ad_connect sys_cpu_resetn pl_sysmon/s_axi_aresetn
ad_cpu_interconnect 0x44A00000 axi_adrv9001
ad_cpu_interconnect 0x44A30000 axi_adrv9001_rx1_dma
ad_cpu_interconnect 0x44A40000 axi_adrv9001_rx2_dma
ad_cpu_interconnect 0x44A50000 axi_adrv9001_tx1_dma
ad_cpu_interconnect 0x44A60000 axi_adrv9001_tx2_dma
ad_cpu_interconnect 0x45000000 axi_sysid_0
ad_cpu_interconnect 0x44A70000 pl_sysmon
ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_rx1_dma/m_dest_axi
ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_rx2_dma/m_dest_axi
ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_tx1_dma/m_src_axi
ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9001_tx2_dma/m_src_axi
ad_connect $sys_dma_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn
ad_connect $sys_dma_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn
ad_connect $sys_dma_resetn axi_adrv9001_tx1_dma/m_src_axi_aresetn
ad_connect $sys_dma_resetn axi_adrv9001_tx2_dma/m_src_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_adrv9001_rx1_dma/irq
ad_cpu_interrupt ps-12 mb-11 axi_adrv9001_rx2_dma/irq
ad_cpu_interrupt ps-11 mb-6 axi_adrv9001_tx1_dma/irq
ad_cpu_interrupt ps-10 mb-5 axi_adrv9001_tx2_dma/irq
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file

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# pluto_ng pinout
set_property -dict {PACKAGE_PIN J7 IOSTANDARD LVCMOS18} [get_ports gp_int] ; ## IO_L24P_65_ADRV9002_GP_INT
set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS18} [get_ports mode] ; ## IO_65_ADRV9002_MODE
set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS18} [get_ports resetb] ; ## IO_65_ADRV9002_RST
set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports clksrc] ; ## IO_66_ADRV9002_CLKSRC
set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS18} [get_ports spi_di] ; ## IO_L2P_65_SPI_DO
set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS18} [get_ports spi_do] ; ## IO_L1N_65_SPI_DI
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS18} [get_ports spi_enb] ; ## IO_65_SPI_ENB
set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L1P_65_SPICLK
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports usb_pd_reset] ; ## IO_66_USB_PD_RESET
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports vin_poe_valid_n] ; ## VIN_POE_VALID_N
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports vin_usb2_valid_n] ; ## VIN_USB2_VALID_N
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports vin_usb1_valid_n] ; ## VIN_USB1_VALID_N
## ADRV9002 # BANK 65
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports rx1_enable] ; ## IO_L2N_65_RX1_EN
set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS18} [get_ports rx2_enable] ; ## IO_L10N_65_RX2_EN
set_property -dict {PACKAGE_PIN K4 IOSTANDARD LVCMOS18} [get_ports tx1_enable] ; ## IO_L23P_65_TX1_EN
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports tx2_enable] ; ## IO_L23N_65_TX2_EN
set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_n] ; ## IO_L11N_65_RX1_DCLK_OUT_N
set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_p] ; ## IO_L11P_65_RX1_DCLK_OUT_P
set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_in_n] ; ## IO_L5N_65_RX1_IDATA_OUT_N
set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_in_p] ; ## IO_L5P_65_RX1_IDATA_OUT_P
set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_in_n] ; ## IO_L6N_65_RX1_QDATA_OUT_N
set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_in_p] ; ## IO_L6P_65_RX1_QDATA_OUT_P
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_in_n] ; ## IO_L4N_65_RX1_STROBE_OUT_N
set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_in_p] ; ## IO_L4P_65_RX1_STROBE_OUT_P
set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_in_n] ; ## IO_L12N_65_RX2_DCLK_OUT_N
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_in_p] ; ## IO_L12P_65_RX2_DCLK_OUT_P
set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_in_n] ; ## IO_L8N_65_RX2_IDATA_OUT_N
set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_in_p] ; ## IO_L8P_65_RX2_IDATA_OUT_P
set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_in_n] ; ## IO_L9N_65_RX2_QDATA_OUT_N
set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_in_p] ; ## IO_L9P_65_RX2_QDATA_OUT_P
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_in_n] ; ## IO_L7N_65_RX2_STROBE_OUT_N
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_in_p] ; ## IO_L7P_65_RX2_STROBE_OUT_P
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVDS} [get_ports tx1_dclk_out_n] ; ## IO_L15N_65_TX1_DCLK_IN_N
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVDS} [get_ports tx1_dclk_out_p] ; ## IO_L15P_65_TX1_DCLK_IN_P
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_in_n] ; ## IO_L13N_65_TX1_DCLK_OUT_N
set_property -dict {PACKAGE_PIN M3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_in_p] ; ## IO_L13P_65_TX1_DCLK_OUT_P
set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVDS} [get_ports tx1_idata_out_n] ; ## IO_L17N_65_TX1_IDATA_IN_N
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVDS} [get_ports tx1_idata_out_p] ; ## IO_L17P_65_TX1_IDATA_IN_P
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVDS} [get_ports tx1_qdata_out_n] ; ## IO_L18N_65_TX1_QDATA_IN_N
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVDS} [get_ports tx1_qdata_out_p] ; ## IO_L18P_65_TX1_QDATA_IN_P
set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVDS} [get_ports tx1_strobe_out_n] ; ## IO_L16N_65_TX1_STROBE_IN_N
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVDS} [get_ports tx1_strobe_out_p] ; ## IO_L16P_65_TX1_STROBE_IN_P
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVDS} [get_ports tx2_dclk_out_n] ; ## IO_L19N_65_TX2_DCLK_IN_N
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVDS} [get_ports tx2_dclk_out_p] ; ## IO_L19P_65_TX2_DCLK_IN_P
set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_in_n] ; ## IO_L14N_65_TX2_DCLK_OUT_N
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_in_p] ; ## IO_L14P_65_TX2_DCLK_OUT_P
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVDS} [get_ports tx2_idata_out_n] ; ## IO_L21N_65_TX2_IDATA_IN_N
set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVDS} [get_ports tx2_idata_out_p] ; ## IO_L21P_65_TX2_IDATA_IN_P
set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVDS} [get_ports tx2_qdata_out_n] ; ## IO_L22N_65_TX2_QDATA_IN_N
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVDS} [get_ports tx2_qdata_out_p] ; ## IO_L22P_65_TX2_QDATA_IN_P
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVDS} [get_ports tx2_strobe_out_n] ; ## IO_L20N_65_TX2_STROBE_IN_N
set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVDS} [get_ports tx2_strobe_out_p] ; ## IO_L20P_65_TX2_STROBE_IN_P
# BANK 64
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_ref_clk_n] ; ## IO_L12N_64_DEV_CLK_IN_N
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_ref_clk_p] ; ## IO_L12P_64_DEV_CLK_IN_P
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_n] ; ## IO_L3N_65_MCS_FPGA_IN_N
set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_p] ; ## IO_L3P_65_MCS_FPGA_IN_P
set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_mcs_in_n] ; ## IO_L11N_64_EXT_MCS_IN_N
set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_mcs_in_p] ; ## IO_L11P_64_EXT_MCS_IN_P
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18} [get_ports dgpio[0]] ; ## IO_L5P_64_ADRV9002_DGPIO_0
set_property -dict {PACKAGE_PIN AD5 IOSTANDARD LVCMOS18} [get_ports dgpio[1]] ; ## IO_L5N_64_ADRV9002_DGPIO_1
set_property -dict {PACKAGE_PIN AC9 IOSTANDARD LVCMOS18} [get_ports dgpio[2]] ; ## IO_L6P_64_ADRV9002_DGPIO_2
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports dgpio[3]] ; ## IO_L6N_64_ADRV9002_DGPIO_3
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS18} [get_ports dgpio[4]] ; ## IO_L7P_64_ADRV9002_DGPIO_4
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS18} [get_ports dgpio[5]] ; ## IO_L7N_64_ADRV9002_DGPIO_5
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports dgpio[6]] ; ## IO_L14N_64_ADRV9002_DGPIO_6
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports dgpio[7]] ; ## IO_T2U_N12_64_ADRV9002_DGPIO_7
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18} [get_ports dgpio[8]] ; ## IO_L9P_64_ADRV9002_DGPIO_8
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS18} [get_ports dgpio[9]] ; ## IO_L9N_64_ADRV9002_DGPIO_9
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18} [get_ports dgpio[10]] ; ## IO_L18N_64_ADRV9002_DGPIO_10
set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVCMOS18} [get_ports dgpio[11]] ; ## IO_L18P_64_ADRV9002_DGPIO_11
#set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports adrv9002_dev_clk] ; ## IO_L13P_64_ADRV9002_DEV_CLK_OUT
#set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS18} [get_ports s_1pps] ; ## IO_L10P_64_1PPS
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18} [get_ports rf_rx1a_mux_ctl] ; ## IO_L15N_RF_RX1A_MUX_CTL
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVCMOS18} [get_ports rf_rx1b_mux_ctl] ; ## IO_L15P_RF_RX1B_MUX_CTL
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports rf_rx2a_mux_ctl] ; ## IO_L14P_RF_RX2A_MUX_CTL
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports rf_rx2b_mux_ctl] ; ## IO_L13P_RF_RX2B_MUX_CTL
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18} [get_ports rf_tx1_mux_ctl1] ; ## IO_L16P_RF_TX1_MUX_CTL1
set_property -dict {PACKAGE_PIN AD3 IOSTANDARD LVCMOS18} [get_ports rf_tx1_mux_ctl2] ; ## IO_L16N_RF_TX1_MUX_CTL2
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVCMOS18} [get_ports rf_tx2_mux_ctl1] ; ## IO_L17P_RF_TX2_MUX_CTL1
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18} [get_ports rf_tx2_mux_ctl2] ; ## IO_L17N_RF_TX2_MUX_CTL2
# EXTERNAL GPIO CONNECTOR # BANK 26 3V3
set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS33} [get_ports ext_gpio[0]]; # IO_L1P_AD11P_26 IO_L1P_AD11P_26
set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports ext_gpio[1]]; # IO_L1N_AD11N_26 IO_L1N_AD11N_26
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports ext_gpio[2]]; # IO_L2P_AD10P_26 IO_L2P_AD10P_26
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS33} [get_ports ext_gpio[3]]; # IO_L2N_AD10N_26 IO_L2N_AD10N_26
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports ext_gpio[4]]; # IO_L3P_AD9P_26 IO_L3P_AD9P_26
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports ext_gpio[5]]; # IO_L3N_AD9N_26 IO_L3N_AD9N_26
set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports ext_gpio[6]]; # IO_L4P_AD8P_26 IO_L4P_AD8P_26
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS33} [get_ports ext_gpio[7]]; # IO_L4N_AD8N_26 IO_L4N_AD8N_26
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS33} [get_ports ext_gpio[8]]; # IO_L5P_AD7P_26 IO_L5P_HDGC_AD7P_26
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports ext_gpio[9]]; # IO_L5N_AD7N_26 IO_L5N_HDGC_AD7N_26
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports ext_gpio[10]]; # IO_L6P_AD6P_26 IO_L6P_HDGC_AD6P_26
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports ext_gpio[11]]; # IO_L6N_AD6N_26 IO_L6N_HDGC_AD6N_26
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS33} [get_ports ext_gpio[12]]; # IO_L7P_AD5P_26 IO_L7P_HDGC_AD5P_26
set_property -dict {PACKAGE_PIN E9 IOSTANDARD LVCMOS33} [get_ports ext_gpio[13]]; # IO_L7N_AD5N_26 IO_L7N_HDGC_AD5N_26
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS33} [get_ports ext_gpio[14]]; # IO_L8P_AD4P_26 IO_L8P_HDGC_AD4P_26
set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS33} [get_ports ext_gpio[15]]; # IO_L8N_AD4N_26 IO_L8N_HDGC_AD4N_26
# add-on board connector
# BANK 26 3V3
set_property -dict {PACKAGE_PIN H10 IOSTANDARD LVCMOS33} [get_ports add_on[0]] ; # IO_L9P_AD3P_26 -
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS33} [get_ports add_on[1]] ; # IO_L9N_AD3N_26 -
set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS33} [get_ports add_on[2]] ; # IO_L10P_AD2P_26 -
set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVCMOS33} [get_ports add_on[3]] ; # IO_L10N_AD2N_26 -
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports add_on[4]] ; # IO_L11P_AD1P_26 -
set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS33} [get_ports add_on[5]] ; # IO_L11N_AD1N_26 -
set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS33} [get_ports add_on[6]] ; # IO_L12P_AD0P_26
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS33} [get_ports add_on[7]] ; # IO_L12N_AD0N_26
# BANK 64 1V8
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports add_on[8]] ; # IO_L1P_T0L_N0_DBC_64 -
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports add_on[9]] ; # IO_L1N_T0L_N1_DBC_64
set_property -dict {PACKAGE_PIN AD8 IOSTANDARD LVCMOS18} [get_ports add_on[10]] ; # IO_L2P_T0L_N2_64
set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVCMOS18} [get_ports add_on[11]] ; # IO_L2N_T0L_N3_64
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18} [get_ports add_on[12]] ; # IO_L21P_T3L_N4_AD8P_64
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18} [get_ports add_on[13]] ; # IO_L21N_T3L_N5_AD8N_64
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18} [get_ports add_on[14]] ; # IO_L23P_T3U_N8_64
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18} [get_ports add_on[15]] ; # IO_L23N_T3U_N9_64
## connect to system management (monitor)
set_property -dict {PACKAGE_PIN G8 IOSTANDARD ANALOG} [get_ports s_1p0_rf_sns_p] ; ## G8 IO_L16P_66_1P0_RF_SNS_P
set_property -dict {PACKAGE_PIN F8 IOSTANDARD ANALOG} [get_ports s_1p0_rf_sns_n] ; ## F8 IO_L16N_66_1P0_RF_SNS_N
set_property -dict {PACKAGE_PIN H6 IOSTANDARD ANALOG} [get_ports s_1p8_rf_sns_p] ; ## H6 IO_L17P_66_1P8_RF_SNS_P
set_property -dict {PACKAGE_PIN G6 IOSTANDARD ANALOG} [get_ports s_1p8_rf_sns_n] ; ## G6 IO_L17N_66_1P8_RF_SNS_N
set_property -dict {PACKAGE_PIN G7 IOSTANDARD ANALOG} [get_ports s_1p3_rf_sns_p] ; ## G7 IO_L18P_66_1P3_RF_SNS_P
set_property -dict {PACKAGE_PIN F7 IOSTANDARD ANALOG} [get_ports s_1p3_rf_sns_n] ; ## F7 IO_L18N_66_1P3_RF_SNS_N
set_property -dict {PACKAGE_PIN A6 IOSTANDARD ANALOG} [get_ports s_5v0_rf_sns_p] ; ## A6 IO_L19P_66_5V0_RF_SNS_P
set_property -dict {PACKAGE_PIN A5 IOSTANDARD ANALOG} [get_ports s_5v0_rf_sns_n] ; ## A5 IO_L19N_66_5V0_RF_SNS_N
set_property -dict {PACKAGE_PIN C8 IOSTANDARD ANALOG} [get_ports s_2v5_sns_p] ; ## C8 IO_L20P_66_2V5_SNS_P
set_property -dict {PACKAGE_PIN B8 IOSTANDARD ANALOG} [get_ports s_2v5_sns_n] ; ## B8 IO_L20N_66_2V5_SNS_N
set_property -dict {PACKAGE_PIN C5 IOSTANDARD ANALOG} [get_ports s_vtt_ps_ddr4_sns_p] ; ## C5 IO_L21P_66_VTT_PS_DDR4_SNS_P
set_property -dict {PACKAGE_PIN B5 IOSTANDARD ANALOG} [get_ports s_vtt_ps_ddr4_sns_n] ; ## B5 IO_L21N_66_VTT_PS_DDR4_SNS_N
set_property -dict {PACKAGE_PIN A9 IOSTANDARD ANALOG} [get_ports s_1v2_ps_ddr4_sns_p] ; ## A9 IO_L22P_66_1V2_PS_DDR4_SNS_P
set_property -dict {PACKAGE_PIN A8 IOSTANDARD ANALOG} [get_ports s_1v2_ps_ddr4_sns_n] ; ## A8 IO_L22N_66_1V2_PS_DDR4_SNS_N
set_property -dict {PACKAGE_PIN G3 IOSTANDARD ANALOG} [get_ports s_0v85_mgtravcc_sns_p] ; ## G3 IO_L4P_66_0V85_MGTRAVCC_SNS_P
set_property -dict {PACKAGE_PIN F3 IOSTANDARD ANALOG} [get_ports s_0v85_mgtravcc_sns_n] ; ## F3 IO_L4N_66_0V85_MGTRAVCC_SNS_N
set_property -dict {PACKAGE_PIN H4 IOSTANDARD ANALOG} [get_ports s_5v0_sns_p] ; ## H4 IO_L6P_66_5V0_SNS_P
set_property -dict {PACKAGE_PIN H3 IOSTANDARD ANALOG} [get_ports s_5v0_sns_n] ; ## H3 IO_L6N_66_5V0_SNS_N
set_property -dict {PACKAGE_PIN A3 IOSTANDARD ANALOG} [get_ports s_1v2_sns_p] ; ## A3 IO_L8P_66_1V2_SNS_P
set_property -dict {PACKAGE_PIN A2 IOSTANDARD ANALOG} [get_ports s_1v2_sns_n] ; ## A2 IO_L8N_66_1V2_SNS_N
set_property -dict {PACKAGE_PIN B3 IOSTANDARD ANALOG} [get_ports s_1v8_mgtravtt_sns_p] ; ## B3 IO_L10P_66_1V8_MGTRAVTT_SNS_P
set_property -dict {PACKAGE_PIN B2 IOSTANDARD ANALOG} [get_ports s_1v8_mgtravtt_sns_n] ; ## B2 IO_L10N_66_1V8_MGTRAVTT_SNS_N
# clocks
create_clock -name spi0_clk -period 100 [get_pins -hier */EMIOSPI0SCLKO]
create_clock -name ref_clk -period 8.00 [get_ports fpga_ref_clk_p]
create_clock -name rx1_dclk_out -period 2.034 [get_ports rx1_dclk_in_p]
create_clock -name rx2_dclk_out -period 2.034 [get_ports rx2_dclk_in_p]
create_clock -name tx1_dclk_out -period 2.034 [get_ports tx1_dclk_in_p]
create_clock -name tx2_dclk_out -period 2.034 [get_ports tx2_dclk_in_p]
set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_1 \
[list [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O]] \
[get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_buf_fast/O]] \
]
set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_2 \
[list [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O]] \
[get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_buf_fast/O]] \
]

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source ../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
# make ADI_PLUTO_FPGA=xczu2cg-sfva625-1-e
# make ADI_PLUTO_FPGA=xczu3eg-sfva625-1-e
if [info exists ::env(ADI_PLUTO_FPGA)] {
set p_device $::env(ADI_PLUTO_FPGA)
} else {
# default
set p_device xczu3eg-sfva625-2-e
}
set sys_zynq 2
adi_project pluto_ng
adi_project_files pluto_ng [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_iobuf.v" ]
adi_project_run pluto_ng

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
output spi_do,
input spi_di,
output spi_clk,
output spi_enb,
output usb_pd_reset,
inout [15:0] ext_gpio,
inout [15:0] add_on,
inout [11:0] dgpio,
input gp_int,
output mode,
output resetb,
output clksrc,
input vin_poe_valid_n,
input vin_usb2_valid_n,
input vin_usb1_valid_n,
input fpga_ref_clk_n,
input fpga_ref_clk_p,
//input adrv9002_dev_clk,
//input s_1pps,
input fpga_mcs_in_n,
input fpga_mcs_in_p,
output dev_mcs_fpga_out_n,
output dev_mcs_fpga_out_p,
input rx1_dclk_in_n,
input rx1_dclk_in_p,
output rx1_enable,
input rx1_idata_in_n,
input rx1_idata_in_p,
input rx1_qdata_in_n,
input rx1_qdata_in_p,
input rx1_strobe_in_n,
input rx1_strobe_in_p,
input rx2_dclk_in_n,
input rx2_dclk_in_p,
output rx2_enable,
input rx2_idata_in_n,
input rx2_idata_in_p,
input rx2_qdata_in_n,
input rx2_qdata_in_p,
input rx2_strobe_in_n,
input rx2_strobe_in_p,
output tx1_dclk_out_n,
output tx1_dclk_out_p,
input tx1_dclk_in_n,
input tx1_dclk_in_p,
output tx1_enable,
output tx1_idata_out_n,
output tx1_idata_out_p,
output tx1_qdata_out_n,
output tx1_qdata_out_p,
output tx1_strobe_out_n,
output tx1_strobe_out_p,
output tx2_dclk_out_n,
output tx2_dclk_out_p,
input tx2_dclk_in_n,
input tx2_dclk_in_p,
output tx2_enable,
output tx2_idata_out_n,
output tx2_idata_out_p,
output tx2_qdata_out_n,
output tx2_qdata_out_p,
output tx2_strobe_out_n,
output tx2_strobe_out_p,
output rf_rx1a_mux_ctl,
output rf_rx1b_mux_ctl,
output rf_rx2a_mux_ctl,
output rf_rx2b_mux_ctl,
output rf_tx1_mux_ctl1,
output rf_tx1_mux_ctl2,
output rf_tx2_mux_ctl1,
output rf_tx2_mux_ctl2,
input s_1p0_rf_sns_p,
input s_1p0_rf_sns_n,
input s_1p8_rf_sns_p,
input s_1p8_rf_sns_n,
input s_1p3_rf_sns_p,
input s_1p3_rf_sns_n,
input s_5v0_rf_sns_p,
input s_5v0_rf_sns_n,
input s_2v5_sns_p,
input s_2v5_sns_n,
input s_vtt_ps_ddr4_sns_p,
input s_vtt_ps_ddr4_sns_n,
input s_1v2_ps_ddr4_sns_p,
input s_1v2_ps_ddr4_sns_n,
input s_0v85_mgtravcc_sns_p,
input s_0v85_mgtravcc_sns_n,
input s_5v0_sns_p,
input s_5v0_sns_n,
input s_1v2_sns_p,
input s_1v2_sns_n,
input s_1v8_mgtravtt_sns_p,
input s_1v8_mgtravtt_sns_n
);
// internal registers
reg mcs_sync_m = 'd0;
reg [31:0] mcs_sync_pulse_period = 32'd1000; // 26us (ref_clk = 38.4M clk)
reg [31:0] mcs_sync_pulse_delay = 32'd4000; // 104.1us (ref_clk = 38.4M clk)
reg [31:0] mcs_sync_pulse_period_cnt = 32'd0;
reg [31:0] mcs_sync_pulse_delay_cnt = 32'd0;
reg [ 2:0] mcs_sync_pulse_num = 3'd0;
reg mcs_sync_busy = 1'b0;
reg mcs_out = 1'b0;
// internal signals
wire [94:0] gpio_i;
wire [94:0] gpio_o;
wire [94:0] gpio_t;
wire spi0_csn;
wire fpga_ref_clk;
wire fpga_mcs_in;
wire mssi_sync;
wire mcs_start;
wire system_sync;
wire mcs_or_system_sync_n;
wire gpio_rx1_enable_in;
wire gpio_rx2_enable_in;
wire gpio_tx1_enable_in;
wire gpio_tx2_enable_in;
// assignments
assign gpio_i[94:64] = gpio_o[94:64];
assign gpio_i[15:7] = gpio_o[15:7];
assign gpio_i[3:1] = gpio_o[3:1];
assign gpio_i[0] = gp_int;
assign clksrc = gpio_o[1];
assign mode = gpio_o[2];
assign resetb = gpio_o[3];
assign gpio_i[4] = vin_poe_valid_n;
assign gpio_i[5] = vin_usb2_valid_n;
assign gpio_i[6] = vin_usb1_valid_n;
assign mssi_sync = mcs_sync_busy | gpio_o[7];
//assign usb_pd_reset = gpio_o[8];
assign rf_rx1a_mux_ctl = gpio_o[ 8];
assign rf_rx1b_mux_ctl = gpio_o[ 9];
assign rf_rx2a_mux_ctl = gpio_o[10];
assign rf_rx2b_mux_ctl = gpio_o[11];
assign rf_tx1_mux_ctl1 = gpio_o[12];
assign rf_tx1_mux_ctl2 = gpio_o[13];
assign rf_tx2_mux_ctl1 = gpio_o[14];
assign rf_tx2_mux_ctl2 = gpio_o[15];
assign spi_enb = spi0_csn;
// instantiations
ad_iobuf #(.DATA_WIDTH(16)) i_ext_gpio_buf (
.dio_t (gpio_t[31:16]),
.dio_i (gpio_o[31:16]),
.dio_o (gpio_i[31:16]),
.dio_p (ext_gpio));
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
.dio_t ({gpio_t[47:32]}),
.dio_i ({gpio_o[47:32]}),
.dio_o ({gpio_i[47:32]}),
.dio_p ({gpio_rx1_enable_in, // 47
gpio_rx2_enable_in, // 46
gpio_tx1_enable_in, // 45
gpio_tx2_enable_in, // 44
dgpio[11:0]})); // 43:32
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf_addon (
.dio_t ({gpio_t[63:48]}),
.dio_i ({gpio_o[63:48]}),
.dio_o ({gpio_i[63:48]}),
.dio_p ({add_on}));
IBUFDS i_ibufgs_fpga_ref_clk (
.I (fpga_ref_clk_p),
.IB (fpga_ref_clk_n),
.O (fpga_ref_clk));
IBUFDS i_ibufgs_fpga_mcs_in (
.I (fpga_mcs_in_p),
.IB (fpga_mcs_in_n),
.O (fpga_mcs_in));
OBUFDS i_obufds_dev_mcs_fpga_in (
.I (mcs_out),
.O (dev_mcs_fpga_out_p),
.OB (dev_mcs_fpga_out_n));
// multi-chip or system synchronization
// consider fpga_ref_clk = 38.4M (26.042n)
// the MCS sync requires 6 pulses of min 10us with a in between delay of min 100us
always @(posedge fpga_ref_clk) begin
mcs_sync_m <= fpga_mcs_in;
if (mcs_start) begin
mcs_sync_busy <= 1'b1;
mcs_sync_pulse_period_cnt <= mcs_sync_pulse_period;
mcs_sync_pulse_delay_cnt <= mcs_sync_pulse_delay;
mcs_sync_pulse_num <= 3'd0;
mcs_out <= 1'b0;
end else if (mcs_sync_busy == 1'b1) begin
if (mcs_sync_pulse_period_cnt != 32'd0) begin
mcs_sync_pulse_period_cnt <= mcs_sync_pulse_period_cnt - 32'd1;
mcs_out <= 1'b1;
end else if (mcs_sync_pulse_delay_cnt != 32'd0) begin
mcs_sync_pulse_delay_cnt <= mcs_sync_pulse_delay_cnt - 32'd1;
mcs_out <= 1'b0;
end else begin
if (mcs_sync_pulse_num < 5) begin
mcs_sync_pulse_num <= mcs_sync_pulse_num + 3'd1;
mcs_sync_pulse_period_cnt <= mcs_sync_pulse_period;
mcs_sync_pulse_delay_cnt <= mcs_sync_pulse_delay;
end else begin
mcs_sync_busy <= 1'b0;
end
mcs_out <= 1'b0;
end
end
end
assign mcs_start = !mcs_sync_m & fpga_mcs_in & !mcs_sync_busy & mcs_or_system_sync_n;
assign system_sync = fpga_mcs_in & !mcs_or_system_sync_n;
assign mcs_or_system_sync_n = gpio_o[64];
system_wrapper i_system_wrapper (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.spi0_csn(spi0_csn),
.spi0_miso(spi_di),
.spi0_mosi(spi_do),
.spi0_sclk(spi_clk),
.ref_clk (fpga_ref_clk),
.mssi_sync (mssi_sync),
.system_sync (system_sync),
.tx_output_enable (1'b1),
.rx1_dclk_in_n (rx1_dclk_in_n),
.rx1_dclk_in_p (rx1_dclk_in_p),
.rx1_idata_in_n (rx1_idata_in_n),
.rx1_idata_in_p (rx1_idata_in_p),
.rx1_qdata_in_n (rx1_qdata_in_n),
.rx1_qdata_in_p (rx1_qdata_in_p),
.rx1_strobe_in_n (rx1_strobe_in_n),
.rx1_strobe_in_p (rx1_strobe_in_p),
.rx2_dclk_in_n (rx2_dclk_in_n),
.rx2_dclk_in_p (rx2_dclk_in_p),
.rx2_idata_in_n (rx2_idata_in_n),
.rx2_idata_in_p (rx2_idata_in_p),
.rx2_qdata_in_n (rx2_qdata_in_n),
.rx2_qdata_in_p (rx2_qdata_in_p),
.rx2_strobe_in_n (rx2_strobe_in_n),
.rx2_strobe_in_p (rx2_strobe_in_p),
.tx1_dclk_out_n (tx1_dclk_out_n),
.tx1_dclk_out_p (tx1_dclk_out_p),
.tx1_dclk_in_n (tx1_dclk_in_n),
.tx1_dclk_in_p (tx1_dclk_in_p),
.tx1_idata_out_n (tx1_idata_out_n),
.tx1_idata_out_p (tx1_idata_out_p),
.tx1_qdata_out_n (tx1_qdata_out_n),
.tx1_qdata_out_p (tx1_qdata_out_p),
.tx1_strobe_out_n (tx1_strobe_out_n),
.tx1_strobe_out_p (tx1_strobe_out_p),
.tx2_dclk_out_n (tx2_dclk_out_n),
.tx2_dclk_out_p (tx2_dclk_out_p),
.tx2_dclk_in_n (tx2_dclk_in_n),
.tx2_dclk_in_p (tx2_dclk_in_p),
.tx2_idata_out_n (tx2_idata_out_n),
.tx2_idata_out_p (tx2_idata_out_p),
.tx2_qdata_out_n (tx2_qdata_out_n),
.tx2_qdata_out_p (tx2_qdata_out_p),
.tx2_strobe_out_n (tx2_strobe_out_n),
.tx2_strobe_out_p (tx2_strobe_out_p),
.rx1_enable (rx1_enable),
.rx2_enable (rx2_enable),
.tx1_enable (tx1_enable),
.tx2_enable (tx2_enable),
.gpio_rx1_enable_in (gpio_rx1_enable_in),
.gpio_rx2_enable_in (gpio_rx2_enable_in),
.gpio_tx1_enable_in (gpio_tx1_enable_in),
.gpio_tx2_enable_in (gpio_tx2_enable_in),
.s_1p0_rf_sns_p (s_1p0_rf_sns_p),
.s_1p0_rf_sns_n (s_1p0_rf_sns_n),
.s_1p8_rf_sns_p (s_1p8_rf_sns_p),
.s_1p8_rf_sns_n (s_1p8_rf_sns_n),
.s_1p3_rf_sns_p (s_1p3_rf_sns_p),
.s_1p3_rf_sns_n (s_1p3_rf_sns_n),
.s_5v0_rf_sns_p (s_5v0_rf_sns_p),
.s_5v0_rf_sns_n (s_5v0_rf_sns_n),
.s_2v5_sns_p (s_2v5_sns_p),
.s_2v5_sns_n (s_2v5_sns_n),
.s_vtt_ps_ddr4_sns_p (s_vtt_ps_ddr4_sns_p),
.s_vtt_ps_ddr4_sns_n (s_vtt_ps_ddr4_sns_n),
.s_1v2_ps_ddr4_sns_p (s_1v2_ps_ddr4_sns_p),
.s_1v2_ps_ddr4_sns_n (s_1v2_ps_ddr4_sns_n),
.s_0v85_mgtravcc_sns_p (s_0v85_mgtravcc_sns_p),
.s_0v85_mgtravcc_sns_n (s_0v85_mgtravcc_sns_n),
.s_5v0_sns_p (s_5v0_sns_p),
.s_5v0_sns_n (s_5v0_sns_n),
.s_1v2_sns_p (s_1v2_sns_p),
.s_1v2_sns_n (s_1v2_sns_n),
.s_1v8_mgtravtt_sns_p (s_1v8_mgtravtt_sns_p),
.s_1v8_mgtravtt_sns_n (s_1v8_mgtravtt_sns_n)
);
endmodule
// ***************************************************************************
// ***************************************************************************