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ad9083: Add reference design for ad9083 eval board

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sergiu arpadi 2020-10-23 16:30:38 +03:00 committed by sarpadi
parent dcec4fe1b7
commit 3dce87d09b
7 changed files with 453 additions and 0 deletions
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6
projects/ad9083_evb/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

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projects/ad9083_evb/common/ad9083_evb_bd.tcl Normal file
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# RX parameters
set RX_NUM_OF_LANES 4 ; # L
set RX_NUM_OF_CONVERTERS 16 ; # M
set RX_SAMPLES_PER_FRAME 1 ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
# fifo size should provide 64ks/ch
# (256*2^16)/16[ch]/16[N/NP]=64ks
set adc_fifo_name axi_ad9083_fifo
set adc_data_width 256
set adc_dma_data_width 256
set adc_fifo_address_width 16
# adc peripherals
# rx_out_clk = ref_clk
# qpll0 selected
ad_ip_instance axi_adxcvr axi_ad9083_rx_xcvr [list \
NUM_OF_LANES $RX_NUM_OF_LANES \
QPLL_ENABLE 1 \
TX_OR_RX_N 0 \
SYS_CLK_SEL 3 \
OUT_CLK_SEL 4 \
]
adi_axi_jesd204_rx_create axi_ad9083_rx_jesd $RX_NUM_OF_LANES
ad_ip_parameter axi_ad9083_rx_jesd/rx CONFIG.SYSREF_IOB false
ad_ip_parameter axi_ad9083_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH 8
ad_ip_instance util_cpack2 util_ad9083_rx_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
adi_tpl_jesd204_rx_create rx_ad9083_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
ad_ip_instance axi_dmac axi_ad9083_rx_dma [list \
DMA_TYPE_SRC 1 \
DMA_TYPE_DEST 0 \
CYCLIC 0 \
SYNC_TRANSFER_START 0 \
DMA_2D_TRANSFER 0 \
MAX_BYTES_PER_BURST 4096 \
AXI_SLICE_DEST 1 \
AXI_SLICE_SRC 1 \
DMA_LENGTH_WIDTH 24 \
DMA_DATA_WIDTH_DEST $adc_dma_data_width \
DMA_DATA_WIDTH_SRC $adc_dma_data_width \
]
# common cores
# fPLLClkin = 500 MHz => RX_CLK25_DIV = 20
# fPLLClkout = 5000 MHz
# VCO = 10000 MHz - qpll0
ad_ip_instance util_adxcvr util_ad9083_xcvr [list \
RX_NUM_OF_LANES $RX_NUM_OF_LANES \
TX_NUM_OF_LANES 0 \
QPLL_FBDIV 40 \
QPLL_REFCLK_DIV 2 \
RX_OUT_DIV 1 \
RX_CLK25_DIV 20 \
POR_CFG 0x0 \
QPLL_CFG0 0x391c \
QPLL_CFG1 0x0000 \
QPLL_CFG1_G3 0x0020 \
QPLL_CFG2 0x0f80 \
QPLL_CFG2_G3 0x0f80 \
QPLL_CFG3 0x0120 \
QPLL_CFG4 0x0002 \
QPLL_CP 0x1f \
QPLL_CP_G3 0x1f \
QPLL_LPF 0x2ff \
CH_HSPMUX 0x2424 \
PREIQ_FREQ_BST 0 \
RXPI_CFG0 0x0002 \
RXPI_CFG1 0x0 \
RXCDR_CFG0 0x3 \
RXCDR_CFG2_GEN2 0x164 \
RXCDR_CFG2_GEN4 0x0 \
RXCDR_CFG3 0x2a \
RXCDR_CFG3_GEN2 0x24 \
RXCDR_CFG3_GEN3 0x0 \
RXCDR_CFG3_GEN4 0x0 \
]
# xcvr interfaces
set rx_ref_clk rx_ref_clk_0
create_bd_port -dir I $rx_ref_clk
create_bd_port -dir I rx_core_clk_0
ad_connect $sys_cpu_resetn util_ad9083_xcvr/up_rstn
ad_connect $sys_cpu_clk util_ad9083_xcvr/up_clk
# Rx
ad_connect ad9083_rx_device_clk rx_core_clk_0
ad_connect ad9083_rx_link_clk util_ad9083_xcvr/rx_out_clk_0
ad_xcvrcon util_ad9083_xcvr axi_ad9083_rx_xcvr axi_ad9083_rx_jesd {} ad9083_rx_link_clk ad9083_rx_device_clk
ad_xcvrpll $rx_ref_clk util_ad9083_xcvr/qpll_ref_clk_0
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_ad9083_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_ad9083_rx_xcvr/up_pll_rst util_ad9083_xcvr/up_cpll_rst_$ch
}
ad_xcvrpll axi_ad9083_rx_xcvr/up_pll_rst util_ad9083_xcvr/up_qpll_rst_*
# connections (adc)
ad_connect $sys_dma_resetn axi_ad9083_rx_dma/m_dest_axi_aresetn
ad_connect ad9083_rx_device_clk_rstgen/peripheral_reset axi_ad9083_fifo/adc_rst
ad_connect ad9083_rx_device_clk axi_ad9083_fifo/adc_clk
ad_connect $sys_dma_clk axi_ad9083_fifo/dma_clk
ad_connect $sys_dma_clk axi_ad9083_rx_dma/s_axis_aclk
ad_connect util_ad9083_rx_cpack/packed_fifo_wr_data axi_ad9083_fifo/adc_wdata
ad_connect util_ad9083_rx_cpack/packed_fifo_wr_en axi_ad9083_fifo/adc_wr
ad_connect axi_ad9083_fifo/dma_wr axi_ad9083_rx_dma/s_axis_valid
ad_connect axi_ad9083_fifo/dma_wdata axi_ad9083_rx_dma/s_axis_data
ad_connect axi_ad9083_fifo/dma_wready axi_ad9083_rx_dma/s_axis_ready
ad_connect axi_ad9083_fifo/dma_xfer_req axi_ad9083_rx_dma/s_axis_xfer_req
ad_connect ad9083_rx_device_clk rx_ad9083_tpl_core/link_clk
ad_connect ad9083_rx_device_clk util_ad9083_rx_cpack/clk
ad_connect ad9083_rx_device_clk_rstgen/peripheral_reset util_ad9083_rx_cpack/reset
ad_connect axi_ad9083_rx_jesd/rx_sof rx_ad9083_tpl_core/link_sof
ad_connect axi_ad9083_rx_jesd/rx_data_tdata rx_ad9083_tpl_core/link_data
ad_connect axi_ad9083_rx_jesd/rx_data_tvalid rx_ad9083_tpl_core/link_valid
ad_connect rx_ad9083_tpl_core/adc_valid_0 util_ad9083_rx_cpack/fifo_wr_en
ad_connect rx_ad9083_tpl_core/adc_dovf util_ad9083_rx_cpack/fifo_wr_overflow
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_ad9083_tpl_core/adc_enable_$i util_ad9083_rx_cpack/enable_$i
ad_connect rx_ad9083_tpl_core/adc_data_$i util_ad9083_rx_cpack/fifo_wr_data_$i
}
# interconnect (cpu)
ad_cpu_interconnect 0x44A00000 rx_ad9083_tpl_core
ad_cpu_interconnect 0x44A60000 axi_ad9083_rx_xcvr
ad_cpu_interconnect 0x44AA0000 axi_ad9083_rx_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9083_rx_dma
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9083_rx_xcvr/m_axi
# interconnect (mem/dac)
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-12 mb-13 axi_ad9083_rx_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9083_rx_dma/irq

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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad9083_evb_zcu102
M_DEPS += ../common/ad9083_evb_bd.tcl
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
LIB_DEPS += util_adcfifo
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += sysid_rom
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source ../common/ad9083_evb_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file

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# ad9083
#input
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports glblclk_p] ; ## FMC_HPC0_LA00_CC_P
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports glblclk_n] ; ## FMC_HPC0_LA00_CC_N
set_property -dict {PACKAGE_PIN G8} [get_ports ref_clk0_p] ; ## FMC_HPC0_GBTCLK0_M2C_C_P
set_property -dict {PACKAGE_PIN G7} [get_ports ref_clk0_n] ; ## FMC_HPC0_GBTCLK0_M2C_C_N
set_property -dict {PACKAGE_PIN H2} [get_ports rx_data_p[0]] ; ## FMC_HPC0_DP0_M2C_P
set_property -dict {PACKAGE_PIN H1} [get_ports rx_data_n[0]] ; ## FMC_HPC0_DP0_M2C_N
set_property -dict {PACKAGE_PIN J4} [get_ports rx_data_p[1]] ; ## FMC_HPC0_DP1_M2C_P
set_property -dict {PACKAGE_PIN J3} [get_ports rx_data_n[1]] ; ## FMC_HPC0_DP1_M2C_N
set_property -dict {PACKAGE_PIN F2} [get_ports rx_data_p[2]] ; ## FMC_HPC0_DP2_M2C_P
set_property -dict {PACKAGE_PIN F1} [get_ports rx_data_n[2]] ; ## FMC_HPC0_DP2_M2C_N
set_property -dict {PACKAGE_PIN K2} [get_ports rx_data_p[3]] ; ## FMC_HPC0_DP3_M2C_P
set_property -dict {PACKAGE_PIN K1} [get_ports rx_data_n[3]] ; ## FMC_HPC0_DP3_M2C_N
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## FMC_HPC0_LA07_N
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## FMC_HPC0_LA02_P
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## FMC_HPC0_LA01_CC_P
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## FMC_HPC0_LA01_CC_N
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports pwdn] ; ## FMC_HPC0_LA02_N
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports rstb] ; ## FMC_HPC0_LA07_P
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18} [get_ports refsel] ; ## FMC_HPC0_LA03_P
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## FMC_HPC0_LA04_P
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## FMC_HPC0_LA04_N
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports sysref_p] ; ## FMC_HPC0_LA08_P
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports sysref_n] ; ## FMC_HPC0_LA08_N
# clocks
create_clock -period 2 -name rx_ref_clk [get_ports ref_clk0_p]
create_clock -period 8 -name rx_ref_clk2 [get_ports glblclk_p]
set_input_delay -clock [get_clocks rx_ref_clk2] [get_property PERIOD [get_clocks rx_ref_clk2]] \
[get_ports -regexp -filter { NAME =~ ".*sysref.*" && DIRECTION == "IN" }]

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projects/ad9083_evb/zcu102/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9083_evb_zcu102
adi_project_files ad9083_fmc_zcu102 [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_3w_spi.v" \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run ad9083_evb_zcu102

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
input ref_clk0_p,
input ref_clk0_n,
input glblclk_p,
input glblclk_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output rx_sync_p,
output rx_sync_n,
input sysref_p,
input sysref_n,
inout pwdn,
inout rstb,
inout refsel,
inout spi_sdio,
output spi_csn_clk,
output spi_csn_adc,
output spi_clk
);
// internal signals
wire [94:0] gpio_i;
wire [94:0] gpio_o;
wire [94:0] gpio_t;
wire [20:0] gpio_bd;
wire ref_clk0;
wire rx_sync;
wire sysref;
wire sysref_s;
wire rx_ref_core_clk0_s;
wire rx_ref_core_clk0;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire spi_miso;
wire spi_mosi;
assign gpio_i[94:35] = gpio_o[94:35];
assign gpio_i[31:21] = gpio_o[31:21];
assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
assign gpio_i[20: 8] = gpio_bd_i;
assign gpio_bd_o = gpio_o[7:0];
assign spi_csn_adc = spi0_csn[0];
assign spi_csn_clk = spi0_csn[1];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
// instantiations
IBUFDS IBUFDS_inst (
.O(rx_ref_core_clk0_s),
.I(glblclk_p),
.IB(glblclk_n)
);
BUFG BUFG_inst (
.O(rx_ref_core_clk0),
.I(rx_ref_core_clk0_s)
);
IBUFDS_GTE4 i_ibufds_ref_clk0 (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
ad_3w_spi #(
.NUM_OF_SLAVES(2))
i_spi (
.spi_csn(spi0_csn[1:0]),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio),
.spi_dir(spidbg_dir)
);
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf (
.dio_t ({gpio_t[34:32]}),
.dio_i ({gpio_o[34:32]}),
.dio_o ({gpio_i[34:32]}),
.dio_p ({refsel, // 34
rstb, // 33
pwdn})); // 32
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
// BUFG i_bufg_gt_sysref(
// .I(sysref_s),
// .O(sysref));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
system_wrapper i_system_wrapper (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk0),
.rx_core_clk_0 (rx_ref_core_clk0),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (sysref),
.spi0_sclk (spi0_clk),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi1_csn (),
.spi1_miso (),
.spi1_mosi (),
.spi1_sclk ()
);
endmodule
// ***************************************************************************