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axi_ad9625: initial release

main
Rejeesh Kutty 2014-06-09 16:39:08 -04:00
parent bef6a9c32c
commit 3e5990366e
5 changed files with 1233 additions and 0 deletions
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312
library/axi_ad9625/axi_ad9625.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9625 (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_dwr,
adc_ddata,
adc_dsync,
adc_dovf,
adc_dunf,
adc_enable,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [255:0] rx_data;
// dma interface
output adc_clk;
output adc_dwr;
output [255:0] adc_ddata;
output adc_dsync;
input adc_dovf;
input adc_dunf;
output adc_enable;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [ 31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [191:0] adc_mon_data;
// internal registers
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [255:0] adc_ddata = 'd0;
reg [ 31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [191:0] adc_data_s;
wire adc_or_s;
wire adc_status_s;
wire [255:0] adc_channel_data_s;
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire [ 31:0] up_adc_channel_rdata_s;
wire up_adc_channel_ack_s;
wire up_sel_s;
wire up_wr_s;
wire [ 13:0] up_addr_s;
wire [ 31:0] up_wdata_s;
wire [ 31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data = adc_data_s;
// adc channels - dma interface
always @(posedge adc_clk) begin
adc_dsync <= 1'b1;
adc_dwr <= 1'b1;
adc_ddata <= adc_channel_data_s;
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_s;
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_s;
end
end
// main (device interface)
axi_ad9625_if i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_status (adc_status_s));
// channel
axi_ad9625_channel i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_enable (adc_enable),
.adc_dfmt_data (adc_channel_data_s),
.up_adc_pn_err (up_adc_pn_err_s),
.up_adc_pn_oos (up_adc_pn_oos_s),
.up_adc_or (up_adc_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_s),
.up_ack (up_adc_channel_ack_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_pn_err_s),
.adc_status_pn_oos (up_adc_pn_oos_s),
.adc_status_or (up_adc_or_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9625/axi_ad9625_channel.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9625_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_enable,
adc_dfmt_data,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// adc interface
input adc_clk;
input adc_rst;
input [191:0] adc_data;
input adc_or;
// channel interface
output adc_enable;
output [255:0] adc_dfmt_data;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_pn_type_s;
// instantiations
axi_ad9625_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_type (adc_pn_type_s));
genvar n;
generate
for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_lb_enb (),
.adc_pn_sel (),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9625/axi_ad9625_if.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9625_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data,
adc_or,
adc_status);
// jesd interface
// rx_clk is ref_clk/4
input rx_clk;
input [255:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [191:0] adc_data;
output adc_or;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [ 15:0] adc_data_s15_s;
wire [ 15:0] adc_data_s14_s;
wire [ 15:0] adc_data_s13_s;
wire [ 15:0] adc_data_s12_s;
wire [ 15:0] adc_data_s11_s;
wire [ 15:0] adc_data_s10_s;
wire [ 15:0] adc_data_s09_s;
wire [ 15:0] adc_data_s08_s;
wire [ 15:0] adc_data_s07_s;
wire [ 15:0] adc_data_s06_s;
wire [ 15:0] adc_data_s05_s;
wire [ 15:0] adc_data_s04_s;
wire [ 15:0] adc_data_s03_s;
wire [ 15:0] adc_data_s02_s;
wire [ 15:0] adc_data_s01_s;
wire [ 15:0] adc_data_s00_s;
wire [ 31:0] rx_data0_s;
wire [ 31:0] rx_data1_s;
wire [ 31:0] rx_data2_s;
wire [ 31:0] rx_data3_s;
wire [ 31:0] rx_data4_s;
wire [ 31:0] rx_data5_s;
wire [ 31:0] rx_data6_s;
wire [ 31:0] rx_data7_s;
assign adc_clk = rx_clk;
assign adc_or = 1'b0;
// samples only
assign adc_data = {adc_data_s15_s[11:0], adc_data_s14_s[11:0],
adc_data_s13_s[11:0], adc_data_s12_s[11:0], adc_data_s11_s[11:0],
adc_data_s10_s[11:0], adc_data_s09_s[11:0], adc_data_s08_s[11:0],
adc_data_s07_s[11:0], adc_data_s06_s[11:0], adc_data_s05_s[11:0],
adc_data_s04_s[11:0], adc_data_s03_s[11:0], adc_data_s02_s[11:0],
adc_data_s01_s[11:0], adc_data_s00_s[11:0]};
// data is received across multiple lanes (reconstruct samples)
assign adc_data_s15_s = {rx_data7_s[27:24], rx_data6_s[31:24], rx_data7_s[31:28]};
assign adc_data_s14_s = {rx_data5_s[27:24], rx_data4_s[31:24], rx_data5_s[31:28]};
assign adc_data_s13_s = {rx_data3_s[27:24], rx_data2_s[31:24], rx_data3_s[31:28]};
assign adc_data_s12_s = {rx_data1_s[27:24], rx_data0_s[31:24], rx_data1_s[31:28]};
assign adc_data_s11_s = {rx_data7_s[19:16], rx_data6_s[23:16], rx_data7_s[23:20]};
assign adc_data_s10_s = {rx_data5_s[19:16], rx_data4_s[23:16], rx_data5_s[23:20]};
assign adc_data_s09_s = {rx_data3_s[19:16], rx_data2_s[23:16], rx_data3_s[23:20]};
assign adc_data_s08_s = {rx_data1_s[19:16], rx_data0_s[23:16], rx_data1_s[23:20]};
assign adc_data_s07_s = {rx_data7_s[11: 8], rx_data6_s[15: 8], rx_data7_s[15:12]};
assign adc_data_s06_s = {rx_data5_s[11: 8], rx_data4_s[15: 8], rx_data5_s[15:12]};
assign adc_data_s05_s = {rx_data3_s[11: 8], rx_data2_s[15: 8], rx_data3_s[15:12]};
assign adc_data_s04_s = {rx_data1_s[11: 8], rx_data0_s[15: 8], rx_data1_s[15:12]};
assign adc_data_s03_s = {rx_data7_s[ 3: 0], rx_data6_s[ 7: 0], rx_data7_s[ 7: 4]};
assign adc_data_s02_s = {rx_data5_s[ 3: 0], rx_data4_s[ 7: 0], rx_data5_s[ 7: 4]};
assign adc_data_s01_s = {rx_data3_s[ 3: 0], rx_data2_s[ 7: 0], rx_data3_s[ 7: 4]};
assign adc_data_s00_s = {rx_data1_s[ 3: 0], rx_data0_s[ 7: 0], rx_data1_s[ 7: 4]};
assign rx_data0_s = rx_data[ 31: 0];
assign rx_data1_s = rx_data[ 63: 32];
assign rx_data2_s = rx_data[ 95: 64];
assign rx_data3_s = rx_data[127: 96];
assign rx_data4_s = rx_data[159:128];
assign rx_data5_s = rx_data[191:160];
assign rx_data6_s = rx_data[223:192];
assign rx_data7_s = rx_data[255:224];
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9625
adi_ip_files axi_ad9625 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9625_pnmon.v" \
"axi_ad9625_channel.v" \
"axi_ad9625_if.v" \
"axi_ad9625.v" ]
adi_ip_properties axi_ad9625
ipx::save_core [ipx::current_core]

558
library/axi_ad9625/axi_ad9625_pnmon.v Executable file
View File

@ -0,0 +1,558 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9625_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type);
// adc interface
input adc_clk;
input [191:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type;
// internal registers
reg [191:0] adc_pn_data = 'd0;
reg adc_pn_match_d_1 = 'd0;
reg adc_pn_match_d_0 = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals
wire [191:0] adc_pn_data_rev_s;
wire [191:0] adc_pn_data_in_s;
wire adc_pn_match_d_1_s;
wire adc_pn_match_d_0_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [191:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// PN23 function
function [191:0] pn23;
input [191:0] din;
reg [191:0] dout;
begin
dout[191] = din[22] ^ din[17];
dout[190] = din[21] ^ din[16];
dout[189] = din[20] ^ din[15];
dout[188] = din[19] ^ din[14];
dout[187] = din[18] ^ din[13];
dout[186] = din[17] ^ din[12];
dout[185] = din[16] ^ din[11];
dout[184] = din[15] ^ din[10];
dout[183] = din[14] ^ din[ 9];
dout[182] = din[13] ^ din[ 8];
dout[181] = din[12] ^ din[ 7];
dout[180] = din[11] ^ din[ 6];
dout[179] = din[10] ^ din[ 5];
dout[178] = din[ 9] ^ din[ 4];
dout[177] = din[ 8] ^ din[ 3];
dout[176] = din[ 7] ^ din[ 2];
dout[175] = din[ 6] ^ din[ 1];
dout[174] = din[ 5] ^ din[ 0];
dout[173] = din[ 4] ^ din[22] ^ din[17];
dout[172] = din[ 3] ^ din[21] ^ din[16];
dout[171] = din[ 2] ^ din[20] ^ din[15];
dout[170] = din[ 1] ^ din[19] ^ din[14];
dout[169] = din[ 0] ^ din[18] ^ din[13];
dout[168] = din[22] ^ din[12];
dout[167] = din[21] ^ din[11];
dout[166] = din[20] ^ din[10];
dout[165] = din[19] ^ din[ 9];
dout[164] = din[18] ^ din[ 8];
dout[163] = din[17] ^ din[ 7];
dout[162] = din[16] ^ din[ 6];
dout[161] = din[15] ^ din[ 5];
dout[160] = din[14] ^ din[ 4];
dout[159] = din[13] ^ din[ 3];
dout[158] = din[12] ^ din[ 2];
dout[157] = din[11] ^ din[ 1];
dout[156] = din[10] ^ din[ 0];
dout[155] = din[ 9] ^ din[22] ^ din[17];
dout[154] = din[ 8] ^ din[21] ^ din[16];
dout[153] = din[ 7] ^ din[20] ^ din[15];
dout[152] = din[ 6] ^ din[19] ^ din[14];
dout[151] = din[ 5] ^ din[18] ^ din[13];
dout[150] = din[ 4] ^ din[17] ^ din[12];
dout[149] = din[ 3] ^ din[16] ^ din[11];
dout[148] = din[ 2] ^ din[15] ^ din[10];
dout[147] = din[ 1] ^ din[14] ^ din[ 9];
dout[146] = din[ 0] ^ din[13] ^ din[ 8];
dout[145] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[144] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[143] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[142] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[141] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[140] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[139] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[138] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[137] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17];
dout[136] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16];
dout[135] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[15];
dout[134] = din[11] ^ din[ 1] ^ din[ 6] ^ din[19] ^ din[14];
dout[133] = din[10] ^ din[ 0] ^ din[ 5] ^ din[18] ^ din[13];
dout[132] = din[ 9] ^ din[22] ^ din[ 4] ^ din[12];
dout[131] = din[ 8] ^ din[21] ^ din[ 3] ^ din[11];
dout[130] = din[ 7] ^ din[20] ^ din[ 2] ^ din[10];
dout[129] = din[ 6] ^ din[19] ^ din[ 1] ^ din[ 9];
dout[128] = din[ 5] ^ din[18] ^ din[ 0] ^ din[ 8];
dout[127] = din[ 4] ^ din[22] ^ din[ 7];
dout[126] = din[ 3] ^ din[21] ^ din[ 6];
dout[125] = din[ 2] ^ din[20] ^ din[ 5];
dout[124] = din[ 1] ^ din[19] ^ din[ 4];
dout[123] = din[ 0] ^ din[18] ^ din[ 3];
dout[122] = din[22] ^ din[ 2];
dout[121] = din[21] ^ din[ 1];
dout[120] = din[20] ^ din[ 0];
dout[119] = din[19] ^ din[22] ^ din[17];
dout[118] = din[18] ^ din[21] ^ din[16];
dout[117] = din[17] ^ din[20] ^ din[15];
dout[116] = din[16] ^ din[19] ^ din[14];
dout[115] = din[15] ^ din[18] ^ din[13];
dout[114] = din[14] ^ din[17] ^ din[12];
dout[113] = din[13] ^ din[16] ^ din[11];
dout[112] = din[12] ^ din[15] ^ din[10];
dout[111] = din[11] ^ din[14] ^ din[ 9];
dout[110] = din[10] ^ din[13] ^ din[ 8];
dout[109] = din[ 9] ^ din[12] ^ din[ 7];
dout[108] = din[ 8] ^ din[11] ^ din[ 6];
dout[107] = din[ 7] ^ din[10] ^ din[ 5];
dout[106] = din[ 6] ^ din[ 9] ^ din[ 4];
dout[105] = din[ 5] ^ din[ 8] ^ din[ 3];
dout[104] = din[ 4] ^ din[ 7] ^ din[ 2];
dout[103] = din[ 3] ^ din[ 6] ^ din[ 1];
dout[102] = din[ 2] ^ din[ 5] ^ din[ 0];
dout[101] = din[ 1] ^ din[ 4] ^ din[22] ^ din[17];
dout[100] = din[ 0] ^ din[ 3] ^ din[21] ^ din[16];
dout[ 99] = din[22] ^ din[ 2] ^ din[17] ^ din[20] ^ din[15];
dout[ 98] = din[21] ^ din[ 1] ^ din[16] ^ din[19] ^ din[14];
dout[ 97] = din[20] ^ din[ 0] ^ din[15] ^ din[18] ^ din[13];
dout[ 96] = din[19] ^ din[22] ^ din[14] ^ din[12];
dout[ 95] = din[18] ^ din[21] ^ din[13] ^ din[11];
dout[ 94] = din[17] ^ din[20] ^ din[12] ^ din[10];
dout[ 93] = din[16] ^ din[19] ^ din[11] ^ din[ 9];
dout[ 92] = din[15] ^ din[18] ^ din[10] ^ din[ 8];
dout[ 91] = din[14] ^ din[17] ^ din[ 9] ^ din[ 7];
dout[ 90] = din[13] ^ din[16] ^ din[ 8] ^ din[ 6];
dout[ 89] = din[12] ^ din[15] ^ din[ 7] ^ din[ 5];
dout[ 88] = din[11] ^ din[14] ^ din[ 6] ^ din[ 4];
dout[ 87] = din[10] ^ din[13] ^ din[ 5] ^ din[ 3];
dout[ 86] = din[ 9] ^ din[12] ^ din[ 4] ^ din[ 2];
dout[ 85] = din[ 8] ^ din[11] ^ din[ 3] ^ din[ 1];
dout[ 84] = din[ 7] ^ din[10] ^ din[ 2] ^ din[ 0];
dout[ 83] = din[ 6] ^ din[ 9] ^ din[ 1] ^ din[22] ^ din[17];
dout[ 82] = din[ 5] ^ din[ 8] ^ din[ 0] ^ din[21] ^ din[16];
dout[ 81] = din[ 4] ^ din[ 7] ^ din[22] ^ din[17] ^ din[20] ^ din[15];
dout[ 80] = din[ 3] ^ din[ 6] ^ din[21] ^ din[16] ^ din[19] ^ din[14];
dout[ 79] = din[ 2] ^ din[ 5] ^ din[20] ^ din[15] ^ din[18] ^ din[13];
dout[ 78] = din[ 1] ^ din[ 4] ^ din[17] ^ din[19] ^ din[14] ^ din[12];
dout[ 77] = din[ 0] ^ din[ 3] ^ din[16] ^ din[18] ^ din[13] ^ din[11];
dout[ 76] = din[22] ^ din[ 2] ^ din[15] ^ din[12] ^ din[10];
dout[ 75] = din[21] ^ din[ 1] ^ din[14] ^ din[11] ^ din[ 9];
dout[ 74] = din[20] ^ din[ 0] ^ din[13] ^ din[10] ^ din[ 8];
dout[ 73] = din[19] ^ din[22] ^ din[12] ^ din[17] ^ din[ 9] ^ din[ 7];
dout[ 72] = din[18] ^ din[21] ^ din[11] ^ din[16] ^ din[ 8] ^ din[ 6];
dout[ 71] = din[17] ^ din[20] ^ din[10] ^ din[15] ^ din[ 7] ^ din[ 5];
dout[ 70] = din[16] ^ din[19] ^ din[ 9] ^ din[14] ^ din[ 6] ^ din[ 4];
dout[ 69] = din[15] ^ din[18] ^ din[ 8] ^ din[13] ^ din[ 5] ^ din[ 3];
dout[ 68] = din[14] ^ din[17] ^ din[ 7] ^ din[12] ^ din[ 4] ^ din[ 2];
dout[ 67] = din[13] ^ din[16] ^ din[ 6] ^ din[11] ^ din[ 3] ^ din[ 1];
dout[ 66] = din[12] ^ din[15] ^ din[ 5] ^ din[10] ^ din[ 2] ^ din[ 0];
dout[ 65] = din[11] ^ din[14] ^ din[ 4] ^ din[ 9] ^ din[ 1] ^ din[22] ^ din[17];
dout[ 64] = din[10] ^ din[13] ^ din[ 3] ^ din[ 8] ^ din[ 0] ^ din[21] ^ din[16];
dout[ 63] = din[ 9] ^ din[12] ^ din[ 2] ^ din[ 7] ^ din[22] ^ din[17] ^ din[20] ^ din[15];
dout[ 62] = din[ 8] ^ din[11] ^ din[ 1] ^ din[ 6] ^ din[21] ^ din[16] ^ din[19] ^ din[14];
dout[ 61] = din[ 7] ^ din[10] ^ din[ 0] ^ din[ 5] ^ din[20] ^ din[15] ^ din[18] ^ din[13];
dout[ 60] = din[ 6] ^ din[ 9] ^ din[22] ^ din[ 4] ^ din[19] ^ din[14] ^ din[12];
dout[ 59] = din[ 5] ^ din[ 8] ^ din[21] ^ din[ 3] ^ din[18] ^ din[13] ^ din[11];
dout[ 58] = din[ 4] ^ din[ 7] ^ din[17] ^ din[20] ^ din[ 2] ^ din[12] ^ din[10];
dout[ 57] = din[ 3] ^ din[ 6] ^ din[16] ^ din[19] ^ din[ 1] ^ din[11] ^ din[ 9];
dout[ 56] = din[ 2] ^ din[ 5] ^ din[15] ^ din[18] ^ din[ 0] ^ din[10] ^ din[ 8];
dout[ 55] = din[ 1] ^ din[ 4] ^ din[14] ^ din[22] ^ din[ 9] ^ din[ 7];
dout[ 54] = din[ 0] ^ din[ 3] ^ din[13] ^ din[21] ^ din[ 8] ^ din[ 6];
dout[ 53] = din[22] ^ din[ 2] ^ din[12] ^ din[17] ^ din[20] ^ din[ 7] ^ din[ 5];
dout[ 52] = din[21] ^ din[ 1] ^ din[11] ^ din[16] ^ din[19] ^ din[ 6] ^ din[ 4];
dout[ 51] = din[20] ^ din[ 0] ^ din[10] ^ din[15] ^ din[18] ^ din[ 5] ^ din[ 3];
dout[ 50] = din[19] ^ din[22] ^ din[ 9] ^ din[14] ^ din[ 4] ^ din[ 2];
dout[ 49] = din[18] ^ din[21] ^ din[ 8] ^ din[13] ^ din[ 3] ^ din[ 1];
dout[ 48] = din[17] ^ din[20] ^ din[ 7] ^ din[12] ^ din[ 2] ^ din[ 0];
dout[ 47] = din[16] ^ din[19] ^ din[ 6] ^ din[11] ^ din[ 1] ^ din[22] ^ din[17];
dout[ 46] = din[15] ^ din[18] ^ din[ 5] ^ din[10] ^ din[ 0] ^ din[21] ^ din[16];
dout[ 45] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[20] ^ din[15];
dout[ 44] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[19] ^ din[14];
dout[ 43] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[18] ^ din[13];
dout[ 42] = din[11] ^ din[ 1] ^ din[17] ^ din[ 6] ^ din[19] ^ din[12];
dout[ 41] = din[10] ^ din[ 0] ^ din[16] ^ din[ 5] ^ din[18] ^ din[11];
dout[ 40] = din[ 9] ^ din[22] ^ din[15] ^ din[ 4] ^ din[10];
dout[ 39] = din[ 8] ^ din[21] ^ din[14] ^ din[ 3] ^ din[ 9];
dout[ 38] = din[ 7] ^ din[20] ^ din[13] ^ din[ 2] ^ din[ 8];
dout[ 37] = din[ 6] ^ din[19] ^ din[12] ^ din[ 1] ^ din[ 7];
dout[ 36] = din[ 5] ^ din[18] ^ din[11] ^ din[ 0] ^ din[ 6];
dout[ 35] = din[ 4] ^ din[10] ^ din[22] ^ din[ 5];
dout[ 34] = din[ 3] ^ din[ 9] ^ din[21] ^ din[ 4];
dout[ 33] = din[ 2] ^ din[ 8] ^ din[20] ^ din[ 3];
dout[ 32] = din[ 1] ^ din[ 7] ^ din[19] ^ din[ 2];
dout[ 31] = din[ 0] ^ din[ 6] ^ din[18] ^ din[ 1];
dout[ 30] = din[22] ^ din[ 5] ^ din[ 0];
dout[ 29] = din[21] ^ din[ 4] ^ din[22] ^ din[17];
dout[ 28] = din[20] ^ din[ 3] ^ din[21] ^ din[16];
dout[ 27] = din[19] ^ din[ 2] ^ din[20] ^ din[15];
dout[ 26] = din[18] ^ din[ 1] ^ din[19] ^ din[14];
dout[ 25] = din[17] ^ din[ 0] ^ din[18] ^ din[13];
dout[ 24] = din[16] ^ din[22] ^ din[12];
dout[ 23] = din[15] ^ din[21] ^ din[11];
dout[ 22] = din[14] ^ din[20] ^ din[10];
dout[ 21] = din[13] ^ din[19] ^ din[ 9];
dout[ 20] = din[12] ^ din[18] ^ din[ 8];
dout[ 19] = din[11] ^ din[17] ^ din[ 7];
dout[ 18] = din[10] ^ din[16] ^ din[ 6];
dout[ 17] = din[ 9] ^ din[15] ^ din[ 5];
dout[ 16] = din[ 8] ^ din[14] ^ din[ 4];
dout[ 15] = din[ 7] ^ din[13] ^ din[ 3];
dout[ 14] = din[ 6] ^ din[12] ^ din[ 2];
dout[ 13] = din[ 5] ^ din[11] ^ din[ 1];
dout[ 12] = din[ 4] ^ din[10] ^ din[ 0];
dout[ 11] = din[ 3] ^ din[ 9] ^ din[22] ^ din[17];
dout[ 10] = din[ 2] ^ din[ 8] ^ din[21] ^ din[16];
dout[ 9] = din[ 1] ^ din[ 7] ^ din[20] ^ din[15];
dout[ 8] = din[ 0] ^ din[ 6] ^ din[19] ^ din[14];
dout[ 7] = din[22] ^ din[ 5] ^ din[17] ^ din[18] ^ din[13];
dout[ 6] = din[21] ^ din[ 4] ^ din[17] ^ din[16] ^ din[12];
dout[ 5] = din[20] ^ din[ 3] ^ din[16] ^ din[15] ^ din[11];
dout[ 4] = din[19] ^ din[ 2] ^ din[15] ^ din[14] ^ din[10];
dout[ 3] = din[18] ^ din[ 1] ^ din[14] ^ din[13] ^ din[ 9];
dout[ 2] = din[17] ^ din[ 0] ^ din[13] ^ din[12] ^ din[ 8];
dout[ 1] = din[16] ^ din[22] ^ din[12] ^ din[11] ^ din[17] ^ din[ 7];
dout[ 0] = din[15] ^ din[21] ^ din[11] ^ din[10] ^ din[16] ^ din[ 6];
pn23 = dout;
end
endfunction
// PN9 function
function [191:0] pn9;
input [191:0] din;
reg [191:0] dout;
begin
dout[191] = din[ 8] ^ din[ 4];
dout[190] = din[ 7] ^ din[ 3];
dout[189] = din[ 6] ^ din[ 2];
dout[188] = din[ 5] ^ din[ 1];
dout[187] = din[ 4] ^ din[ 0];
dout[186] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[185] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[184] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[183] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[182] = din[ 8] ^ din[ 0];
dout[181] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[180] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[179] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[178] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[177] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[176] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[175] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[174] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[173] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[172] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[171] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[170] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[169] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[168] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[167] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[166] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[165] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[164] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[163] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[162] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[161] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[160] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[159] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[158] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[157] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[156] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[155] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[154] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[153] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[152] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[151] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
dout[150] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
dout[149] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
dout[148] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
dout[147] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
dout[146] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
dout[145] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[144] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[143] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[142] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[141] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[140] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[139] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[138] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6];
dout[137] = din[ 3] ^ din[ 8] ^ din[ 5];
dout[136] = din[ 2] ^ din[ 4] ^ din[ 7];
dout[135] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[134] = din[ 0] ^ din[ 2] ^ din[ 5];
dout[133] = din[ 8] ^ din[ 1];
dout[132] = din[ 7] ^ din[ 0];
dout[131] = din[ 6] ^ din[ 8] ^ din[ 4];
dout[130] = din[ 5] ^ din[ 7] ^ din[ 3];
dout[129] = din[ 4] ^ din[ 6] ^ din[ 2];
dout[128] = din[ 3] ^ din[ 5] ^ din[ 1];
dout[127] = din[ 2] ^ din[ 4] ^ din[ 0];
dout[126] = din[ 1] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[125] = din[ 0] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[124] = din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[123] = din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[122] = din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 0];
dout[121] = din[ 5] ^ din[ 7] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[120] = din[ 4] ^ din[ 6] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[119] = din[ 3] ^ din[ 5] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[118] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[117] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 0];
dout[116] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[115] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[114] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[113] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[112] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 0];
dout[111] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 8];
dout[110] = din[ 5] ^ din[ 4] ^ din[ 6] ^ din[ 1] ^ din[ 0] ^ din[ 7];
dout[109] = din[ 3] ^ din[ 5] ^ din[ 0] ^ din[ 8] ^ din[ 6];
dout[108] = din[ 2] ^ din[ 8] ^ din[ 7] ^ din[ 5];
dout[107] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 6];
dout[106] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[105] = din[ 8] ^ din[ 2] ^ din[ 5];
dout[104] = din[ 4] ^ din[ 7] ^ din[ 1];
dout[103] = din[ 3] ^ din[ 6] ^ din[ 0];
dout[102] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
dout[101] = din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[100] = din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 99] = din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1];
dout[ 98] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[ 97] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 96] = din[ 8] ^ din[ 2] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 95] = din[ 4] ^ din[ 7] ^ din[ 1] ^ din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 94] = din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1];
dout[ 93] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 1] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[ 92] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[ 91] = din[ 0] ^ din[ 6] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 7];
dout[ 90] = din[ 8] ^ din[ 5] ^ din[ 7] ^ din[ 3] ^ din[ 0] ^ din[ 6];
dout[ 89] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8] ^ din[ 5];
dout[ 88] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[ 87] = din[ 5] ^ din[ 4] ^ din[ 3] ^ din[ 0] ^ din[ 6];
dout[ 86] = din[ 3] ^ din[ 2] ^ din[ 8] ^ din[ 5];
dout[ 85] = din[ 2] ^ din[ 4] ^ din[ 1] ^ din[ 7];
dout[ 84] = din[ 1] ^ din[ 3] ^ din[ 0] ^ din[ 6];
dout[ 83] = din[ 0] ^ din[ 2] ^ din[ 8] ^ din[ 4] ^ din[ 5];
dout[ 82] = din[ 8] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 81] = din[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 80] = din[ 6] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1];
dout[ 79] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 3] ^ din[ 0];
dout[ 78] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 8];
dout[ 77] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 7];
dout[ 76] = din[ 4] ^ din[ 1] ^ din[ 0] ^ din[ 6];
dout[ 75] = din[ 3] ^ din[ 0] ^ din[ 8] ^ din[ 5] ^ din[ 4];
dout[ 74] = din[ 2] ^ din[ 8] ^ din[ 7] ^ din[ 3];
dout[ 73] = din[ 1] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[ 72] = din[ 0] ^ din[ 6] ^ din[ 5] ^ din[ 1];
dout[ 71] = din[ 8] ^ din[ 5] ^ din[ 0];
dout[ 70] = din[ 7] ^ din[ 8];
dout[ 69] = din[ 6] ^ din[ 7];
dout[ 68] = din[ 5] ^ din[ 6];
dout[ 67] = din[ 4] ^ din[ 5];
dout[ 66] = din[ 3] ^ din[ 4];
dout[ 65] = din[ 2] ^ din[ 3];
dout[ 64] = din[ 1] ^ din[ 2];
dout[ 63] = din[ 0] ^ din[ 1];
dout[ 62] = din[ 8] ^ din[ 0] ^ din[ 4];
dout[ 61] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 4];
dout[ 60] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 3];
dout[ 59] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 2];
dout[ 58] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 1];
dout[ 57] = din[ 3] ^ din[ 8] ^ din[ 0];
dout[ 56] = din[ 2] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 55] = din[ 1] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[ 54] = din[ 0] ^ din[ 5] ^ din[ 6] ^ din[ 2];
dout[ 53] = din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 52] = din[ 7] ^ din[ 4] ^ din[ 0];
dout[ 51] = din[ 6] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[ 50] = din[ 5] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[ 49] = din[ 4] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 48] = din[ 3] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 47] = din[ 2] ^ din[ 8] ^ din[ 0];
dout[ 46] = din[ 1] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 45] = din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 3];
dout[ 44] = din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[ 43] = din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[ 42] = din[ 6] ^ din[ 3] ^ din[ 4] ^ din[ 2] ^ din[ 0];
dout[ 41] = din[ 5] ^ din[ 2] ^ din[ 3] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[ 40] = din[ 4] ^ din[ 1] ^ din[ 2] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[ 39] = din[ 3] ^ din[ 0] ^ din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2];
dout[ 38] = din[ 2] ^ din[ 8] ^ din[ 0] ^ din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[ 37] = din[ 1] ^ din[ 7] ^ din[ 8] ^ din[ 6] ^ din[ 3] ^ din[ 2] ^ din[ 0];
dout[ 36] = din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 5] ^ din[ 2] ^ din[ 1] ^ din[ 8] ^ din[ 4];
dout[ 35] = din[ 8] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 0] ^ din[ 7] ^ din[ 3];
dout[ 34] = din[ 7] ^ din[ 5] ^ din[ 0] ^ din[ 8] ^ din[ 6] ^ din[ 2];
dout[ 33] = din[ 6] ^ din[ 8] ^ din[ 7] ^ din[ 5] ^ din[ 1];
dout[ 32] = din[ 5] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 0];
dout[ 31] = din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 8];
dout[ 30] = din[ 4] ^ din[ 2] ^ din[ 5] ^ din[ 7];
dout[ 29] = din[ 4] ^ din[ 3] ^ din[ 1] ^ din[ 6];
dout[ 28] = din[ 3] ^ din[ 2] ^ din[ 0] ^ din[ 5];
dout[ 27] = din[ 2] ^ din[ 1] ^ din[ 8];
dout[ 26] = din[ 1] ^ din[ 0] ^ din[ 7];
dout[ 25] = din[ 0] ^ din[ 8] ^ din[ 6] ^ din[ 4];
dout[ 24] = din[ 8] ^ din[ 7] ^ din[ 5] ^ din[ 4] ^ din[ 3];
dout[ 23] = din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3] ^ din[ 2];
dout[ 22] = din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 2] ^ din[ 1];
dout[ 21] = din[ 4] ^ din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 0];
dout[ 20] = din[ 3] ^ din[ 1] ^ din[ 0] ^ din[ 8];
dout[ 19] = din[ 2] ^ din[ 0] ^ din[ 8] ^ din[ 7] ^ din[ 4];
dout[ 18] = din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3];
dout[ 17] = din[ 0] ^ din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 2];
dout[ 16] = din[ 8] ^ din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[ 15] = din[ 7] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 0];
dout[ 14] = din[ 6] ^ din[ 3] ^ din[ 0] ^ din[ 8];
dout[ 13] = din[ 5] ^ din[ 2] ^ din[ 8] ^ din[ 4] ^ din[ 7];
dout[ 12] = din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3] ^ din[ 6];
dout[ 11] = din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
dout[ 10] = din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 9] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 8] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 7] = din[ 8] ^ din[ 2] ^ din[ 5] ^ din[ 4] ^ din[ 7] ^ din[ 3];
dout[ 6] = din[ 7] ^ din[ 4] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[ 5] = din[ 6] ^ din[ 3] ^ din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[ 4] = din[ 5] ^ din[ 2] ^ din[ 8] ^ din[ 1] ^ din[ 0];
dout[ 3] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 8];
dout[ 2] = din[ 0] ^ din[ 6] ^ din[ 8] ^ din[ 4] ^ din[ 7];
dout[ 1] = din[ 8] ^ din[ 5] ^ din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 6];
dout[ 0] = din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3] ^ din[ 2] ^ din[ 5];
pn9 = dout;
end
endfunction
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_rev_s = {adc_data[ 11: 0], adc_data[ 23: 12],
adc_data[ 35: 24], adc_data[ 47: 36], adc_data[ 59: 48], adc_data[ 71: 60],
adc_data[ 83: 72], adc_data[ 95: 84], adc_data[107: 96], adc_data[119:108],
adc_data[131:120], adc_data[143:132], adc_data[155:144], adc_data[167:156],
adc_data[179:168], adc_data[191:180]};
assign adc_pn_data_in_s = adc_pn_data_rev_s ^ {{16{12'h800}}};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[191: 96] == adc_pn_data[191: 96]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[ 95: 0] == adc_pn_data[ 95: 0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 192'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
always @(posedge adc_clk) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
adc_pn_match_d_1 <= adc_pn_match_d_1_s;
adc_pn_match_d_0 <= adc_pn_match_d_0_s;
adc_pn_match_z <= adc_pn_match_z_s;
adc_pn_err <= adc_pn_err_s;
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************