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axi_dmac: Add clock signal spec for m_axis/s_axis bus 

This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Lars-Peter Clausen 2014-09-30 10:46:27 +02:00 committed by Istvan Csomortani
parent 7a9e694446
commit 3e6f553ce3
1 changed files with 6 additions and 6 deletions
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12
library/axi_dmac/axi_dmac_ip.tcl
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@ -39,17 +39,17 @@ set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]] [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
adi_add_bus "s_axis" "axis" "slave" \ adi_add_bus "s_axis" "axis" "slave" \
[list {"s_axis_aclk" "ACLK"} \ [list {"s_axis_ready" "TREADY"} \
{"s_axis_ready" "TREADY"} \ {"s_axis_valid" "TVALID"} \
{"s_axis_valid" "VALID"} \
{"s_axis_data" "TDATA"} \ {"s_axis_data" "TDATA"} \
{"s_axis_user" "TUSER"} ] {"s_axis_user" "TUSER"} ]
adi_add_bus_clock "s_axis_aclk" "s_axis"
adi_add_bus "m_axis" "axis" "master" \ adi_add_bus "m_axis" "axis" "master" \
[list {"m_axis_aclk" "ACLK"} \ [list {"m_axis_ready" "TREADY"} \
{"m_axis_ready" "TREADY"} \ {"m_axis_valid" "TVALID"} \
{"m_axis_valid" "VALID"} \
{"m_axis_data" "TDATA"} ] {"m_axis_data" "TDATA"} ]
adi_add_bus_clock "m_axis_aclk" "m_axis"
adi_set_bus_dependency "m_src_axi" "m_src_axi" \ adi_set_bus_dependency "m_src_axi" "m_src_axi" \
"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 0)" "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 0)"