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avl_dacfifo: Cosmetic changes

main
Istvan Csomortani 2017-05-23 14:14:02 +03:00
parent 154e936a4b
commit 3ee7ed7375
3 changed files with 15 additions and 11 deletions
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17
library/altera/avl_dacfifo/avl_dacfifo.v
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@ -86,6 +86,7 @@ module avl_dacfifo #(
// internal signals
wire dma_ready_wr_s;
wire dma_ready_bypass_s;
wire avl_read_s;
wire avl_write_s;
wire [(AVL_DATA_WIDTH-1):0] avl_writedata_s;
@ -102,6 +103,7 @@ module avl_dacfifo #(
wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;
wire dac_xfer_fifo_out_s;
wire dac_dunf_fifo_s;
wire dac_dunf_bypass_s;
avl_dacfifo_wr #(
.AVL_DATA_WIDTH (AVL_DATA_WIDTH),
@ -116,7 +118,6 @@ module avl_dacfifo #(
.dma_valid (dma_valid),
.dma_xfer_req (dma_xfer_req),
.dma_xfer_last (dma_xfer_last),
.dma_last_beat (),
.avl_last_address (avl_last_address_s),
.avl_last_byteenable (avl_last_byteenable_s),
.avl_clk (avl_clk),
@ -164,14 +165,14 @@ module avl_dacfifo #(
end
always @(posedge avl_clk) begin
if (avl_reset == 1) begin
avl_xfer_wren <= 0;
if (avl_reset == 1'b1) begin
avl_xfer_wren <= 1'b0;
end else begin
if (avl_dma_xfer_req == 1) begin
avl_xfer_wren <= 1;
if (avl_dma_xfer_req == 1'b1) begin
avl_xfer_wren <= 1'b1;
end
if (avl_xfer_out_s == 1) begin
avl_xfer_wren <= 0;
if (avl_xfer_out_s == 1'b1) begin
avl_xfer_wren <= 1'b0;
end
end
end
@ -272,7 +273,7 @@ module avl_dacfifo #(
.DELAY_CYCLES(3)
) i_delay (
.clk(dac_clk),
.reset(dac_reset),
.reset(dac_rst),
.din(dac_xfer_out_int),
.dout(dac_xfer_out));

8
library/altera/avl_dacfifo/avl_dacfifo_rd.v
View File

@ -104,11 +104,11 @@ module avl_dacfifo_rd #(
wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_s;
wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_address_diff_s;
wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_wr_address_b2g_s;
wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_address_diff_s;
wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_wr_address_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address_g2b_s;
wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_wr_address_b2g_s;
wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_g2b_s;
wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_rd_address_b2g_s;
wire dac_mem_rd_enable_s;
@ -116,6 +116,9 @@ module avl_dacfifo_rd #(
wire [MEM_WIDTH_DIFF-1:0] avl_last_beats_s;
wire avl_last_transfer_s;
wire avl_read_en_s;
wire avl_mem_wr_enable_s;
wire avl_last_readdatavalid_s;
// ==========================================================================
// An asymmetric memory to transfer data from Avalon interface to DAC
@ -295,13 +298,14 @@ module avl_dacfifo_rd #(
.din (dac_mem_wr_address_m2),
.dout (dac_mem_wr_address_g2b_s));
assign avl_last_readdatavalid_s = (avl_last_transfer & avl_readdatavalid);
always @(posedge dac_clk) begin
if (dac_reset == 1'b1) begin
dac_avl_last_transfer_m1 <= 0;
dac_avl_last_transfer_m2 <= 0;
dac_avl_last_transfer <= 0;
end else begin
dac_avl_last_transfer_m1 <= (avl_last_transfer & avl_readdatavalid);
dac_avl_last_transfer_m1 <= avl_last_readdatavalid_s;
dac_avl_last_transfer_m2 <= dac_avl_last_transfer_m1;
dac_avl_last_transfer <= dac_avl_last_transfer_m2;
end

1
library/altera/avl_dacfifo/avl_dacfifo_wr.v
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@ -38,7 +38,6 @@ module avl_dacfifo_wr #(
input dma_valid,
input dma_xfer_req,
input dma_xfer_last,
output reg [ 3:0] dma_last_beat,
input avl_clk,
input avl_reset,