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arradio/c5soc- clocking changes

main
Rejeesh Kutty 2017-07-20 13:04:56 -04:00
parent a63e268d6e
commit 3ef00475bc
1 changed files with 1 additions and 8 deletions
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9
projects/arradio/c5soc/system_constr.sdc
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@ -6,6 +6,7 @@ derive_pll_clocks
derive_clock_uncertainty
create_clock -period 4.0 -name v_rx_clk
create_generated_clock -name v_tx_clk -source [get_ports {rx_clk_in}] [get_ports {tx_clk_out}]
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
@ -36,14 +37,6 @@ set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_dat
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
create_generated_clock -name v_tx_clk_reg \
-source [get_pins -hierarchical *counter\[0\]*divclk*] \
[get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*]
create_generated_clock -name v_tx_clk \
-source [get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*] \
[get_ports {tx_clk_out}]
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]