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ad9082/vck190: Add initial design 

ADC Mode 27: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS
DAC Mode 35: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
main
Bogdan Luncan 2023-05-11 12:03:25 +01:00 committed by Bogdan Luncan
parent 80fe536863
commit 3f0a487b2e
3 changed files with 112 additions and 0 deletions
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projects/ad9082_fmca_ebz/vck190/Makefile Normal file
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad9082_fmca_ebz_vck190
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/xilinx/data_offload_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
M_DEPS += ../../common/vmk180/vmk180_system_bd.tcl
M_DEPS += ../../common/vck190/vck190_system_constr.xdc
M_DEPS += ../../common/vck190/vck190_system_bd.tcl
M_DEPS += ../../ad9081_fmca_ebz/vck190/timing_constr.xdc
M_DEPS += ../../ad9081_fmca_ebz/vck190/system_top.v
M_DEPS += ../../ad9081_fmca_ebz/vck190/system_constr.xdc
M_DEPS += ../../ad9081_fmca_ebz/vck190/system_bd.tcl
M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl
M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_3w_spi.v
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += axi_tdd
LIB_DEPS += data_offload
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx
LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx
LIB_DEPS += sysid_rom
LIB_DEPS += util_adcfifo
LIB_DEPS += util_dacfifo
LIB_DEPS += util_do_ram
LIB_DEPS += util_hbm
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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projects/ad9082_fmca_ebz/vck190/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/vck190/system_bd.tcl

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projects/ad9082_fmca_ebz/vck190/system_project.tcl Normal file
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source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
# get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1
# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1
#
# Parameter description:
# JESD_MODE : Used link layer encoder mode
# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
#
# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA )
# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE )
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_S : Number of samples per frame
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
# [RX/TX]_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M)
# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=8 RX_JESD_S=4 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=8 TX_JESD_S=4 TX_JESD_NP=12
adi_project ad9082_fmca_ebz_vck190 0 [list \
JESD_MODE [get_env_param JESD_MODE 64B66B ]\
RX_LANE_RATE [get_env_param RX_LANE_RATE 24.75 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 24.75 ] \
REF_CLK_RATE [get_env_param REF_CLK_RATE 375 ] \
RX_JESD_M [get_env_param RX_JESD_M 4 ] \
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
RX_JESD_S [get_env_param RX_JESD_S 4 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 12 ] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 4 ] \
TX_JESD_L [get_env_param TX_JESD_L 8 ] \
TX_JESD_S [get_env_param TX_JESD_S 4 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 12 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \
TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \
]
adi_project_files ad9082_fmca_ebz_vck190 [list \
"../../ad9081_fmca_ebz/vck190/system_top.v" \
"../../ad9081_fmca_ebz/vck190/system_constr.xdc" \
"../../ad9081_fmca_ebz/vck190/timing_constr.xdc" \
"../../../library/common/ad_3w_spi.v" \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ]
set_property strategy Performance_Explore [get_runs impl_1]
adi_project_run ad9082_fmca_ebz_vck190