zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

daq2/a10gx- project/constraint updates

main
Rejeesh Kutty 2017-06-06 16:09:15 -04:00
parent dd48929327
commit 3f92381bd0
2 changed files with 10 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
projects/daq2/a10gx/system_constr.sdc
View File

@ -4,17 +4,8 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_tx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_tx_ctl_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_csr_inst*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_ctl_inst*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]

15
projects/daq2/a10gx/system_project.tcl
View File

@ -1,17 +1,14 @@
load_package flow
source ../../scripts/adi_env.tcl
project_new daq2_a10gx -overwrite
source ../../scripts/adi_project_alt.tcl
source "../../common/a10gx/a10gx_system_assign.tcl"
adi_project_altera daq2_a10gx
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
# files
set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top
# lane interface