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adrv9361- add adl5904

main
Rejeesh Kutty 2017-08-24 15:16:18 -04:00
parent e4988aa131
commit 4050f5ae58
3 changed files with 97 additions and 38 deletions
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78
library/common/ad_adl5904_rst.v Normal file
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@ -0,0 +1,78 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_adl5904_rst (
input sys_cpu_clk,
input rf_peak_det_n,
output rf_peak_rst);
// internal registers
reg rf_peak_det_n_d = 'd0;
reg rf_peak_det_enb_d = 'd0;
reg rf_peak_rst_enb = 'd0;
reg rf_peak_rst_int = 'd0;
// internal signals
wire rf_peak_det_enb_s;
wire rf_peak_rst_1_s;
wire rf_peak_rst_0_s;
// adl5904 input protection
assign rf_peak_rst = rf_peak_rst_int;
assign rf_peak_det_enb_s = ~(rf_peak_det_n_d & rf_peak_det_n);
assign rf_peak_rst_1_s = ~rf_peak_det_enb_d & rf_peak_det_enb_s;
assign rf_peak_rst_0_s = rf_peak_det_enb_d & ~rf_peak_det_enb_s;
always @(posedge sys_cpu_clk) begin
rf_peak_det_n_d <= rf_peak_det_n;
rf_peak_det_enb_d <= rf_peak_det_enb_s;
if (rf_peak_rst_1_s == 1'b1) begin
rf_peak_rst_enb <= 1'b1;
end else if (rf_peak_rst_0_s == 1'b1) begin
rf_peak_rst_enb <= 1'b0;
end
rf_peak_rst_int = ~rf_peak_rst_int & rf_peak_rst_enb;
end
endmodule
// ***************************************************************************
// ***************************************************************************

1
projects/adrv9361z7035/ccfmc_lvds/system_project.tcl
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@ -7,6 +7,7 @@ set p_device "xc7z035ifbg676-2L"
adi_project_xilinx adrv9361z7035_ccfmc_lvds
adi_project_files adrv9361z7035_ccfmc_lvds [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_adl5904_rst.v" \
"../common/adrv9361z7035_constr.xdc" \
"../common/adrv9361z7035_constr_lvds.xdc" \
"../common/ccfmc_constr.xdc" \

56
projects/adrv9361z7035/ccfmc_lvds/system_top.v
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@ -138,9 +138,9 @@ module system_top (
inout tdd_sync,
inout gpio_rf0,
inout gpio_rf1,
output gpio_rf1,
output gpio_rf2,
inout gpio_rf3,
input gpio_rf3,
input gpio_rf4,
inout gpio_rfpwr_enable,
inout gpio_clksel,
@ -155,13 +155,6 @@ module system_top (
output spi_mosi,
input spi_miso);
// internal registers
reg rf_peak_det_n_d = 'd0;
reg rf_peak_det_enb_d = 'd0;
reg rf_peak_rst_enb = 'd0;
reg rf_peak_rst = 'd0;
// internal signals
wire [ 1:0] spi_csn_s;
@ -181,10 +174,6 @@ module system_top (
wire tdd_sync_i;
wire tdd_sync_o;
wire tdd_sync_t;
wire rf_peak_det_n;
wire rf_peak_det_enb;
wire rf_peak_rst_1;
wire rf_peak_rst_0;
// assignments
@ -246,41 +235,20 @@ module system_top (
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
// ad9361 input protection
assign gpio_rf2 = rf_peak_rst;
assign rf_peak_det_n = gpio_rf4;
assign rf_peak_det_enb = ~(rf_peak_det_n_d & rf_peak_det_n);
assign rf_peak_rst_1 = ~rf_peak_det_enb_d & rf_peak_det_enb;
assign rf_peak_rst_0 = rf_peak_det_enb_d & ~rf_peak_det_enb;
always @(posedge sys_cpu_clk) begin
rf_peak_det_n_d <= rf_peak_det_n;
rf_peak_det_enb_d <= rf_peak_det_enb;
if (rf_peak_rst_1 == 1'b1) begin
rf_peak_rst_enb <= 1'b1;
end else if (rf_peak_rst_0 == 1'b1) begin
rf_peak_rst_enb <= 1'b0;
end
rf_peak_rst = ~rf_peak_rst & rf_peak_rst_enb;
end
// ad9361 gpio - 63-32
assign gpio_i[63:62] = gpio_o[63:62];
assign gpio_i[50:47] = gpio_o[50:47];
ad_iobuf #(.DATA_WIDTH(24)) i_iobuf (
.dio_t ({gpio_t[60:55], gpio_t[53:51], gpio_t[46:32]}),
.dio_i ({gpio_o[60:55], gpio_o[53:51], gpio_o[46:32]}),
.dio_o ({gpio_i[60:55], gpio_i[53:51], gpio_i[46:32]}),
ad_iobuf #(.DATA_WIDTH(22)) i_iobuf (
.dio_t ({gpio_t[60:56], gpio_t[52:51], gpio_t[46:32]}),
.dio_i ({gpio_o[60:56], gpio_o[52:51], gpio_o[46:32]}),
.dio_o ({gpio_i[60:56], gpio_i[52:51], gpio_i[46:32]}),
.dio_p ({ ad9517_pdn, // 60:60
ad9517_ref_sel, // 59:59
ad9517_ld, // 58:58
ad9517_status, // 57:57
gpio_rf0, // 56:56
gpio_rf1, // 55:55
gpio_rf3, // 53:53
gpio_rfpwr_enable, // 52:52
gpio_clksel, // 51:51
gpio_resetb, // 46:46
@ -289,6 +257,18 @@ module system_top (
gpio_ctl, // 43:40
gpio_status})); // 39:32
// ad9361 input protection
ad_adl5904_rst i_adl5904_rst_a (
.sys_cpu_clk (sys_cpu_clk),
.rf_peak_det_n (gpio_rf4),
.rf_peak_rst (gpio_rf2));
ad_adl5904_rst i_adl5904_rst_b (
.sys_cpu_clk (sys_cpu_clk),
.rf_peak_det_n (gpio_rf3),
.rf_peak_rst (gpio_rf1));
// instantiations
system_wrapper i_system_wrapper (