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adrv9371x/a10gx- alt 16.1 updates

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Rejeesh Kutty 2017-06-07 09:19:03 -04:00
parent 83747ddb33
commit 40bfd0380e
1 changed files with 6 additions and 0 deletions
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6
projects/adrv9371x/a10gx/system_constr.sdc
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@ -4,7 +4,13 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]
if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} {
set_max_delay -from [get_clocks *sys_ddr3_cntrl_phy_clk_l*] -to [get_clocks *sys_ddr3_cntrl_core_usr_clk*] 0.150
set_min_delay -from [get_clocks *sys_ddr3_cntrl_phy_clk_l*] -to [get_clocks *sys_ddr3_cntrl_core_usr_clk*] 0.000
}