ad_ip_jesd204_tpl_adc: make PN monitor more generic
parent
c34a304d3c
commit
41413a8ffe
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@ -43,12 +43,16 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
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localparam DW = DATA_PATH_WIDTH*CHANNEL_WIDTH-1;
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// Max width of largest PN and data width
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localparam PN_W = DW > 22 ? DW : 22;
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// internal registers
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reg [DW:0] pn_data_pn = 'd0;
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reg [PN_W:0] pn_data_pn = 'd0;
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// internal signals
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wire [DW:0] pn_data_pn_s;
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wire [PN_W:0] pn_data_pn_s;
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wire [DW:0] pn_data_in_s;
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wire [PN_W:0] pn_data_init;
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wire [DW:0] pn23;
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wire [DW+23:0] full_state_pn23;
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@ -56,8 +60,18 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
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wire [DW+9:0] full_state_pn9;
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// pn sequence select
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generate if (PN_W > DW) begin
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reg [PN_W-DW-1:0] pn_data_in_d = 'd0;
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always @(posedge clk) begin
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pn_data_in_d <= pn_data_in_s[PN_W-DW-1:0];
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end
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assign pn_data_init = {pn_data_in_d, pn_data_in_s};
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end else begin
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assign pn_data_init = pn_data_in_s;
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end
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endgenerate
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assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_in_s : pn_data_pn;
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assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_init : pn_data_pn;
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wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0;
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@ -84,12 +98,13 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
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always @(posedge clk) begin
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if (pn_seq_sel == 4'd0) begin
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pn_data_pn <= pn9;
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pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn9} : pn9;
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end else begin
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pn_data_pn <= pn23;
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pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn23} : pn23;
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end
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end
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// pn oos & pn err
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ad_pnmon #(
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@ -98,7 +113,7 @@ module ad_ip_jesd204_tpl_adc_pnmon #(
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.adc_clk (clk),
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.adc_valid_in (1'b1),
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.adc_data_in (pn_data_in_s),
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.adc_data_pn (pn_data_pn),
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.adc_data_pn (pn_data_pn[DW:0]),
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.adc_pn_oos (pn_oos),
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.adc_pn_err (pn_err)
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);
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