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axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled

main
Laszlo Nagy 2021-11-25 17:55:40 +02:00 committed by Laszlo Nagy
parent dfe153dc68
commit 41525f348b
1 changed files with 5 additions and 25 deletions
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30
library/axi_adrv9001/axi_adrv9001_core.v
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@ -563,6 +563,7 @@ module axi_ad9001_core #(
up_delay_cntrl #( up_delay_cntrl #(
.DATA_WIDTH(NUM_LANES), .DATA_WIDTH(NUM_LANES),
.DRP_WIDTH(DRP_WIDTH), .DRP_WIDTH(DRP_WIDTH),
.DISABLE(DISABLE_RX2_SSI),
.BASE_ADDRESS(6'h06)) .BASE_ADDRESS(6'h06))
i_delay_cntrl_rx2 ( i_delay_cntrl_rx2 (
.delay_clk (delay_clk), .delay_clk (delay_clk),
@ -582,15 +583,13 @@ module axi_ad9001_core #(
.up_rdata (up_rdata_s[5]), .up_rdata (up_rdata_s[5]),
.up_rack (up_rack_s[5])); .up_rack (up_rack_s[5]));
generate
if (TDD_DISABLE == 0) begin
wire tdd_rx2_rf_en_loc; wire tdd_rx2_rf_en_loc;
wire tdd_tx2_rf_en_loc; wire tdd_tx2_rf_en_loc;
wire tdd_if2_mode_loc; wire tdd_if2_mode_loc;
axi_adrv9001_tdd #( axi_adrv9001_tdd #(
.BASE_ADDRESS (6'h12) .BASE_ADDRESS (6'h12),
.ENABLED (TDD_DISABLE==0)
) i_tdd_1 ( ) i_tdd_1 (
.clk (rx1_clk), .clk (rx1_clk),
.rst (rx1_rst), .rst (rx1_rst),
@ -616,7 +615,8 @@ module axi_ad9001_core #(
.up_rack (up_rack_s[6])); .up_rack (up_rack_s[6]));
axi_adrv9001_tdd #( axi_adrv9001_tdd #(
.BASE_ADDRESS (6'h13) .BASE_ADDRESS (6'h13),
.ENABLED(TDD_DISABLE == 0 && (DISABLE_RX2_SSI == 0 || DISABLE_TX2_SSI == 0))
) i_tdd_2 ( ) i_tdd_2 (
.clk (rx2_clk), .clk (rx2_clk),
.rst (rx2_rst_loc), .rst (rx2_rst_loc),
@ -647,25 +647,5 @@ module axi_ad9001_core #(
assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2; assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2;
end else begin
assign up_wack_s[6] = 1'b0;
assign up_rack_s[6] = 1'b0;
assign up_rdata_s[6] = 32'h0;
assign up_wack_s[7] = 1'b0;
assign up_rack_s[7] = 1'b0;
assign up_rdata_s[7] = 32'h0;
assign tdd_rx1_rf_en = 1'b1;
assign tdd_tx1_rf_en = 1'b1;
assign tdd_if1_mode = 1'b0;
assign tdd_tx1_valid = 1'b1;
assign tdd_rx1_valid = 1'b1;
assign tdd_rx2_rf_en = 1'b1;
assign tdd_tx2_rf_en = 1'b1;
assign tdd_if2_mode = 1'b0;
assign tdd_tx2_valid = 1'b1;
assign tdd_rx2_valid = 1'b1;
end
endgenerate
endmodule endmodule