adi_project.tcl: Add comments to all proc
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@ -1,34 +1,50 @@
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variable p_board
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variable p_device
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variable sys_zynq
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variable p_prcfg_init
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variable p_prcfg_list
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variable p_prcfg_status
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## Define the supported tool version
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if {![info exists REQUIRED_VIVADO_VERSION]} {
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set REQUIRED_VIVADO_VERSION "2018.3"
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}
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## Define the ADI_IGNORE_VERSION_CHECK environment variable to skip version check
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if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
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set IGNORE_VERSION_CHECK 1
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} elseif {![info exists IGNORE_VERSION_CHECK]} {
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set IGNORE_VERSION_CHECK 0
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}
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## Define the ADI_USE_OOC_SYNTHESIS environment variable to enable out of context
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# synthesis
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if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} {
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set ADI_USE_OOC_SYNTHESIS 1
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} elseif {![info exists ADI_USE_OOC_SYNTHESIS]} {
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set ADI_USE_OOC_SYNTHESIS 0
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}
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## Set to enable incremental compilation
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set ADI_USE_INCR_COMP 1
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## Set to enable power optimization
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set ADI_POWER_OPTIMIZATION 0
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## Initialize global variables
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set p_board "not-applicable"
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set p_device "none"
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set sys_zynq 1
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set ADI_POWER_OPTIMIZATION 0
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set p_prcfg_init ""
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set p_prcfg_list ""
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set p_prcfg_status ""
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## Creates a Xilinx project.
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#
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# \param[project_name] - name of the project
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# \param[mode] - if set non-project mode will be used, otherwise project mode
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# flow, see UG892 for more information
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# \param[parameter_list] - a list of global parameters (parameters of the
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# system_top module)
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#
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# Supported carrier names are: ac701, kc705, vc707, vcu118, kcu105, zed,
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# microzed, zc702, zc706, mitx405, zcu102.
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#
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proc adi_project_xilinx {project_name {mode 0} {parameter_list {}} } {
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global ad_hdl_dir
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@ -186,13 +202,24 @@ proc adi_project_xilinx {project_name {mode 0} {parameter_list {}} } {
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}
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## Add source files to an exiting project.
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#
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# \param[project_name] - name of the project
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# \param[project_files] - list of project files
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#
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proc adi_project_files {project_name project_files} {
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add_files -norecurse -fileset sources_1 $project_files
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# NOTE: top file name is always system_top
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set_property top system_top [current_fileset]
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}
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## Run an existing project (generate bit stream).
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#
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# \param[project_name] - name of the project
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#
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proc adi_project_run {project_name} {
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global ADI_POWER_OPTIMIZATION
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global ADI_USE_OOC_SYNTHESIS
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@ -240,6 +267,13 @@ proc adi_project_run {project_name} {
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}
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}
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## Run synthesis on an partial design; use it in Partial Reconfiguration flow.
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#
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# \param[project_name] - project name
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# \param[prcfg_name] - name of the partial design
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# \param[hdl_files] - hdl source of the partial design
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# \param[xdc_files] - XDC constraint source of the partial design
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#
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proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
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global p_device
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@ -266,6 +300,13 @@ proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
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}
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}
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## Run implementation on an partial design; use it in Partial Reconfiguration
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# flow.
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#
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# \param[project_name] - project name
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# \param[prcfg_name] - name of the partial design
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# \param[xdc_files] - XDC constraint source of the partial design
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#
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proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
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global p_device
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@ -330,9 +371,16 @@ proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
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}
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}
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## Verify an implemented partial reconfiguration design, checks if all the
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# partial design are compatible with the base design.
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#
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# \param[project_name] - project name
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#
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proc adi_project_verify {project_name} {
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# checkpoint for the default design
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global p_prcfg_init
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# list of checkpoints with all the PRs integrated into the default design
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global p_prcfg_list
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global p_prcfg_status
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