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intel/adi_jesd204: Enable master clock generation block for S10 H-Tile

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Filip Gherman 2022-05-17 01:07:48 +03:00 committed by Adrian Costina
parent 19249b51db
commit 4257a47b7a
1 changed files with 11 additions and 0 deletions
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11
library/intel/adi_jesd204/adi_jesd204_hw.tcl
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@ -235,6 +235,17 @@ proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes
} elseif {$device_family == "Stratix 10"} { } elseif {$device_family == "Stratix 10"} {
add_instance lane_pll altera_xcvr_atx_pll_s10_htile add_instance lane_pll altera_xcvr_atx_pll_s10_htile
set_instance_parameter_value lane_pll {rcfg_enable} {1} set_instance_parameter_value lane_pll {rcfg_enable} {1}
if {$num_lanes > 6} {
set_instance_parameter_value lane_pll enable_mcgb {true}
if {$bonding_clocks_en} {
set_instance_parameter_value lane_pll {enable_bonding_clks} {true}
set_instance_parameter_value lane_pll {mcgb_div} {1}
set_instance_parameter_value lane_pll {set_ref_clk_div} {1}
set_instance_parameter_value lane_pll {pma_width} {40}
} else {
set_instance_parameter_value lane_pll enable_hfreq_clk {true}
}
}
## tie pll_select to GND ## tie pll_select to GND
add_instance glue adi_jesd204_glue add_instance glue adi_jesd204_glue