From 427f85959c466d4e36dc73094e76d334f6f161f3 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 29 Apr 2016 16:34:34 +0300 Subject: [PATCH] axi_ad7616: Fix the AXI stream interface --- library/axi_ad7616/axi_ad7616_pif.v | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/library/axi_ad7616/axi_ad7616_pif.v b/library/axi_ad7616/axi_ad7616_pif.v index 4a114f147..ea04d5ad4 100644 --- a/library/axi_ad7616/axi_ad7616_pif.v +++ b/library/axi_ad7616/axi_ad7616_pif.v @@ -214,8 +214,8 @@ module axi_ad7616_pif ( assign db_o = wr_data; always @(posedge clk) begin - data_out_a <= (rd_db_valid) ? db_i : data_out_a; - data_out_b <= (rd_db_valid) ? data_out_a : data_out_b; + data_out_a <= (transfer_state == CNTRL0_HIGH) ? db_i : data_out_a; + data_out_b <= (transfer_state == CNTRL1_HIGH) ? db_i : data_out_b; rd_valid <= rd_db_valid; end @@ -231,12 +231,13 @@ module axi_ad7616_pif ( // The first valid data is ALWAYS the first sample of a convertion always @(negedge clk) begin - if (end_of_conv == 1'b1) + if (end_of_conv == 1'b1) begin xfer_req_d <= m_axis_xfer_req; + end end - assign m_axis_tdata = rd_data; - assign m_axis_tvalid = xfer_req_d & rd_db_valid & rd_db_valid_div2; + assign m_axis_tdata = {data_out_b, data_out_a}; + assign m_axis_tvalid = xfer_req_d & rd_valid & rd_db_valid_div2; endmodule