From 42a7e87cb3467a494f4bc62b97778c984238f4b8 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 26 Mar 2019 12:37:01 +0000 Subject: [PATCH] axi_dmac: patch xfer_request Once xfer_request is set the DMA must accept samples in the same clock cycle if the fifo_wr_en signal is asserted. If the req_valid asserts faster than the ID gets synchronized over the the xfer request asserts without being ready to accept data. This can lead to overflow assertion when using a FIFO like interface. --- library/axi_dmac/data_mover.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/library/axi_dmac/data_mover.v b/library/axi_dmac/data_mover.v index 17fa8a296..fec0d5e7f 100644 --- a/library/axi_dmac/data_mover.v +++ b/library/axi_dmac/data_mover.v @@ -198,9 +198,11 @@ end // req_ready on the same cycle on which the last load happens. // In case early tlast happens accept the new descriptor only when the rewind // request got accepted. +// In case the data mover is not active accept a new descriptor only when the +// upstream logic incremented its id (pending_burst is set). assign last_load = m_axi_valid && last_eot && eot; assign req_ready = (last_load && ~early_tlast) || - (~active && ~transfer_abort_s) || + ((~active && ~transfer_abort_s) && pending_burst) || (transfer_abort_s && rewind_req_ready); always @(posedge clk) begin @@ -240,7 +242,7 @@ end always @(posedge clk) begin if (resetn == 1'b0) begin active <= 1'b0; - end else if (req_valid == 1'b1) begin + end else if (req_valid == 1'b1 && req_ready == 1'b1) begin active <= 1'b1; end else if (last_load == 1'b1) begin active <= 1'b0;