zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_dmac: patch xfer_request 

Once xfer_request is set the DMA must accept samples in the same clock
cycle if the fifo_wr_en signal is asserted.

If the req_valid asserts faster than the ID gets synchronized over the
the xfer request asserts without being ready to accept data.
This can lead to overflow assertion when using a FIFO like interface.
main
Laszlo Nagy 2019-03-26 12:37:01 +00:00 committed by Laszlo Nagy
parent 6fae37504b
commit 42a7e87cb3
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
library/axi_dmac/data_mover.v
View File

@ -198,9 +198,11 @@ end
// req_ready on the same cycle on which the last load happens. // req_ready on the same cycle on which the last load happens.
// In case early tlast happens accept the new descriptor only when the rewind // In case early tlast happens accept the new descriptor only when the rewind
// request got accepted. // request got accepted.
// In case the data mover is not active accept a new descriptor only when the
// upstream logic incremented its id (pending_burst is set).
assign last_load = m_axi_valid && last_eot && eot; assign last_load = m_axi_valid && last_eot && eot;
assign req_ready = (last_load && ~early_tlast) || assign req_ready = (last_load && ~early_tlast) ||
(~active && ~transfer_abort_s) || ((~active && ~transfer_abort_s) && pending_burst) ||
(transfer_abort_s && rewind_req_ready); (transfer_abort_s && rewind_req_ready);
always @(posedge clk) begin always @(posedge clk) begin
@ -240,7 +242,7 @@ end
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin if (resetn == 1'b0) begin
active <= 1'b0; active <= 1'b0;
end else if (req_valid == 1'b1) begin end else if (req_valid == 1'b1 && req_ready == 1'b1) begin
active <= 1'b1; active <= 1'b1;
end else if (last_load == 1'b1) begin end else if (last_load == 1'b1) begin
active <= 1'b0; active <= 1'b0;