axi_dmac: Only apply CDC constraints if clocks are asynchronous
We really only want to apply the CDC constraints if the clocks are actually
asynchronous. Unfortunately we can't use if ... inside a xdc script. But we
can use expr which has support for a ? b : c if-like expression. We can use
that to create helper variables that contains valid clock when the clock
domains are asynchronous or {} if they are not. Passing {} as
set_false_path/set_max_delay as either the source or destination will cause
it to abort and no constraints will be added.
Also add -quiet parameters to avoid generating warning if the constraints
could not be added.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen
parent
9c249d25ab
commit
42a9da0659
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@ -1,11 +1,19 @@
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set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set src_clk [get_clocks -of_objects [get_ports {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
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set dest_clk [get_clocks -of_objects [get_ports {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
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set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
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set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
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# if ... else does not work in xdc files, but expr, well ok...
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set async_src_to_req_clk [expr {$req_clk != $src_clk ? $src_clk : {}}]
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set async_req_to_src_clk [expr {$req_clk != $src_clk ? $req_clk : {}}]
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set async_dest_to_req_clk [expr {$req_clk != $dest_clk ? $dest_clk : {}}]
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set async_req_to_dest_clk [expr {$req_clk != $dest_clk ? $req_clk : {}}]
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set async_dest_to_src_clk [expr {$src_clk != $dest_clk ? $dest_clk : {}}]
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set async_src_to_dest_clk [expr {$src_clk != $dest_clk ? $src_clk : {}}]
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set_property ASYNC_REG TRUE \
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[get_cells -hier cdc_sync_stage1_reg*] \
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[get_cells -hier cdc_sync_stage2_reg*]
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[get_cells -quiet -hier cdc_sync_stage1_reg*] \
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[get_cells -quiet -hier cdc_sync_stage2_reg*]
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#proc get_flops {name inst} {
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# return [get_cells -hier $name \
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@ -31,18 +39,18 @@ set_property ASYNC_REG TRUE \
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#set_multi_bit_constraints i_sync_dest_request_id $src_clk
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#set_multi_bit_constraints i_sync_req_response_id $dest_clk
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set_max_delay \
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-from $req_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_req_to_src_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay \
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-from $src_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_src_to_dest_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $src_clk] -datapath_only
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set_max_delay \
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-from $dest_clk \
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set_max_delay -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $dest_clk] -datapath_only
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@ -52,21 +60,21 @@ set_max_delay \
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#set_single_bit_cdc_constraints i_sync_status_dest $dest_clk
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#set_single_bit_cdc_constraints i_sync_control_dest $req_clk
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set_false_path \
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-from $src_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_false_path -quiet \
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-from $async_src_to_req_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path \
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-from $req_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_false_path -quiet \
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-from $async_req_to_src_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path \
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-from $dest_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_false_path -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path \
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-from $req_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_false_path -quiet \
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-from $async_req_to_dest_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}]
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#set_fifo_cdc_constraints i_dest_req_fifo $req_clk $dest_clk
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@ -74,55 +82,54 @@ set_false_path \
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#set_fifo_cdc_constraints i_src_req_fifo $req_clk $src_clk
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#set_fifo_cdc_constraints i_src_response_fifo $src_clk $req_clk
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set_max_delay \
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-from $req_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_req_to_dest_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay \
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-from $dest_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $dest_clk] -datapath_only
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set_max_delay \
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-from [get_cells -hier cdc_sync_fifo_ram_reg* \
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set_max_delay -quiet \
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-from [get_cells -quiet -hier cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $dest_clk \
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-to $async_dest_to_req_clk \
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[get_property PERIOD $dest_clk] -datapath_only
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set_max_delay \
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-from $dest_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $dest_clk] -datapath_only
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set_max_delay \
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-from $req_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_req_to_dest_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay \
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-from [get_cells -hier cdc_sync_fifo_ram_reg* \
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set_max_delay -quiet \
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-from [get_cells -quiet -hier cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $req_clk \
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-to $async_req_to_dest_clk \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay \
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-from $req_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_req_to_src_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay \
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-from $src_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_src_to_req_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $src_clk] -datapath_only
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set_max_delay \
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-from [get_cells -hier cdc_sync_fifo_ram_reg* \
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set_max_delay -quiet \
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-from [get_cells -quiet -hier cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $src_clk \
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-to $async_src_to_req_clk \
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[get_property PERIOD $src_clk] -datapath_only
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#set_max_delay \
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# -from $src_clk \
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# -to [get_cells -hier cdc_sync_stage1_reg* \
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@ -141,47 +148,47 @@ set_max_delay \
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#set_max_delay -from [get_flops eot_mem_reg* i_request_arb] -to $src_clk [get_property PERIOD $src_clk] -datapath_only
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#set_max_delay -from [get_flops eot_mem_reg* i_request_arb] -to $dest_clk [get_property PERIOD $dest_clk] -datapath_only
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set_max_delay \
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-from [get_cells -hier eot_mem_reg* \
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set_max_delay -quiet \
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-from [get_cells -quiet -hier eot_mem_reg* \
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-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
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-to $src_clk [get_property PERIOD $src_clk] -datapath_only
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set_max_delay \
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-from [get_cells -hier eot_mem_reg* \
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-to $async_src_to_req_clk [get_property PERIOD $src_clk] -datapath_only
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set_max_delay -quiet \
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-from [get_cells -quiet -hier eot_mem_reg* \
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-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
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-to $dest_clk [get_property PERIOD $dest_clk] -datapath_only
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-to $async_dest_to_req_clk [get_property PERIOD $dest_clk] -datapath_only
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#set_fifo_cdc_constraints i_fifo $src_clk $dest_clk
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set_max_delay \
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-from $src_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_src_to_dest_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $src_clk] -datapath_only
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set_max_delay \
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-from $dest_clk \
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-to [get_cells -hier cdc_sync_stage1_reg* \
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set_max_delay -quiet \
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-from $async_dest_to_src_clk \
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-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $dest_clk] -datapath_only
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# Reset signals
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set_false_path \
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set_false_path -quiet \
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-from $req_clk \
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-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
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# Not sure why, but it seems the built-in constraints for the RAM36B are wrong
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set_max_delay \
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-from $dest_clk \
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set_max_delay -quiet \
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-from $async_dest_to_src_clk \
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-to [get_pins -hier ram_reg/REGCEB -filter {NAME =~ *i_fifo*}] \
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[get_property PERIOD $dest_clk] -datapath_only
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# Ignore timing for debug signals to register map
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set_false_path \
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-from [get_cells -hier cdc_sync_stage2_reg* \
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set_false_path -quiet \
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-from [get_cells -quiet -hier cdc_sync_stage2_reg* \
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-filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \
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-to [get_cells -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier cdc_sync_stage2_reg* \
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-to [get_cells -quiet -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier cdc_sync_stage2_reg* \
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-filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \
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-to [get_cells -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier *id_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
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-to [get_cells -quiet -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \
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-to [get_cells -quiet -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
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