axi_spi_engine: Generate false paths only on ASYNC_CLK mode

library/spi_engine/axi_spi_engine/Makefile

@@ -5,7 +5,7 @@
 
 LIBRARY_NAME := axi_spi_engine
 
-GENERIC_DEPS += axi_spi_engine_constr.xdc
+GENERIC_DEPS += axi_spi_engine_constr.ttcl
 GENERIC_DEPS += axi_spi_engine.v
 
 XILINX_DEPS += ../../common/ad_rst.v

library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl

@@ -1,3 +1,11 @@
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
+
+<: if { $async_spi_clk } { :>
 
 set_property ASYNC_REG TRUE \
   [get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
@@ -18,3 +26,4 @@ set_false_path -quiet \
   -from [get_cells -quiet -hierarchical -filter {NAME =~ *offload0_mem_reset_reg* && IS_SEQUENTIAL}] \
   -to [get_cells -quiet -hierarchical -filter {NAME =~ *cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
 
+<: } :>

library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl

@@ -7,11 +7,12 @@ adi_ip_create axi_spi_engine
 adi_ip_files axi_spi_engine [list \
   "$ad_hdl_dir/library/common/up_axi.v" \
   "$ad_hdl_dir/library/common/ad_rst.v" \
-  "axi_spi_engine_constr.xdc" \
+  "axi_spi_engine_constr.ttcl" \
   "axi_spi_engine.v" \
 ]
 
 adi_ip_properties axi_spi_engine
+adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl"
 
 adi_ip_add_core_dependencies { \
 	analog.com:user:util_axis_fifo:1.0 \