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axi/util_adxcvr: Add GTYE4 transceiver support

main
Istvan Csomortani 2019-02-11 17:15:51 +00:00 committed by Adrian Costina
parent 7ce39c4000
commit 42d2738a30
7 changed files with 1108 additions and 42 deletions
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2
library/scripts/adi_xilinx_device_info_enc.tcl
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@ -112,7 +112,7 @@ set xcvr_type_list { \
{ GTYE3_NOT_SUPPORTED 6 } \
{ GTRE4_NOT_SUPPORTED 7 } \
{ GTHE4 8 } \
{ GTYE4_NOT_SUPPORTED 9 } \
{ GTYE4 9 } \
{ GTME4_NOT_SUPPORTED 10}}
set fpga_voltage_list {0 5000} ;# 0 to 5000mV

36
library/xilinx/axi_adxcvr/axi_adxcvr.v
View File

@ -52,7 +52,7 @@ module axi_adxcvr #(
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 3:0] TX_DIFFCTRL = 4'd8,
parameter [ 4:0] TX_DIFFCTRL = 5'd8,
parameter [ 4:0] TX_POSTCURSOR = 5'd0,
parameter [ 4:0] TX_PRECURSOR = 5'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
@ -81,7 +81,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_0,
output [ 1:0] up_ch_sys_clk_sel_0,
output [ 2:0] up_ch_out_clk_sel_0,
output [ 3:0] up_ch_tx_diffctrl_0,
output [ 4:0] up_ch_tx_diffctrl_0,
output [ 4:0] up_ch_tx_postcursor_0,
output [ 4:0] up_ch_tx_precursor_0,
output up_ch_enb_0,
@ -107,7 +107,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_1,
output [ 1:0] up_ch_sys_clk_sel_1,
output [ 2:0] up_ch_out_clk_sel_1,
output [ 3:0] up_ch_tx_diffctrl_1,
output [ 4:0] up_ch_tx_diffctrl_1,
output [ 4:0] up_ch_tx_postcursor_1,
output [ 4:0] up_ch_tx_precursor_1,
output up_ch_enb_1,
@ -133,7 +133,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_2,
output [ 1:0] up_ch_sys_clk_sel_2,
output [ 2:0] up_ch_out_clk_sel_2,
output [ 3:0] up_ch_tx_diffctrl_2,
output [ 4:0] up_ch_tx_diffctrl_2,
output [ 4:0] up_ch_tx_postcursor_2,
output [ 4:0] up_ch_tx_precursor_2,
output up_ch_enb_2,
@ -159,7 +159,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_3,
output [ 1:0] up_ch_sys_clk_sel_3,
output [ 2:0] up_ch_out_clk_sel_3,
output [ 3:0] up_ch_tx_diffctrl_3,
output [ 4:0] up_ch_tx_diffctrl_3,
output [ 4:0] up_ch_tx_postcursor_3,
output [ 4:0] up_ch_tx_precursor_3,
output up_ch_enb_3,
@ -192,7 +192,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_4,
output [ 1:0] up_ch_sys_clk_sel_4,
output [ 2:0] up_ch_out_clk_sel_4,
output [ 3:0] up_ch_tx_diffctrl_4,
output [ 4:0] up_ch_tx_diffctrl_4,
output [ 4:0] up_ch_tx_postcursor_4,
output [ 4:0] up_ch_tx_precursor_4,
output up_ch_enb_4,
@ -218,7 +218,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_5,
output [ 1:0] up_ch_sys_clk_sel_5,
output [ 2:0] up_ch_out_clk_sel_5,
output [ 3:0] up_ch_tx_diffctrl_5,
output [ 4:0] up_ch_tx_diffctrl_5,
output [ 4:0] up_ch_tx_postcursor_5,
output [ 4:0] up_ch_tx_precursor_5,
output up_ch_enb_5,
@ -244,7 +244,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_6,
output [ 1:0] up_ch_sys_clk_sel_6,
output [ 2:0] up_ch_out_clk_sel_6,
output [ 3:0] up_ch_tx_diffctrl_6,
output [ 4:0] up_ch_tx_diffctrl_6,
output [ 4:0] up_ch_tx_postcursor_6,
output [ 4:0] up_ch_tx_precursor_6,
output up_ch_enb_6,
@ -270,7 +270,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_7,
output [ 1:0] up_ch_sys_clk_sel_7,
output [ 2:0] up_ch_out_clk_sel_7,
output [ 3:0] up_ch_tx_diffctrl_7,
output [ 4:0] up_ch_tx_diffctrl_7,
output [ 4:0] up_ch_tx_postcursor_7,
output [ 4:0] up_ch_tx_precursor_7,
output up_ch_enb_7,
@ -303,7 +303,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_8,
output [ 1:0] up_ch_sys_clk_sel_8,
output [ 2:0] up_ch_out_clk_sel_8,
output [ 3:0] up_ch_tx_diffctrl_8,
output [ 4:0] up_ch_tx_diffctrl_8,
output [ 4:0] up_ch_tx_postcursor_8,
output [ 4:0] up_ch_tx_precursor_8,
output up_ch_enb_8,
@ -329,7 +329,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_9,
output [ 1:0] up_ch_sys_clk_sel_9,
output [ 2:0] up_ch_out_clk_sel_9,
output [ 3:0] up_ch_tx_diffctrl_9,
output [ 4:0] up_ch_tx_diffctrl_9,
output [ 4:0] up_ch_tx_postcursor_9,
output [ 4:0] up_ch_tx_precursor_9,
output up_ch_enb_9,
@ -355,7 +355,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_10,
output [ 1:0] up_ch_sys_clk_sel_10,
output [ 2:0] up_ch_out_clk_sel_10,
output [ 3:0] up_ch_tx_diffctrl_10,
output [ 4:0] up_ch_tx_diffctrl_10,
output [ 4:0] up_ch_tx_postcursor_10,
output [ 4:0] up_ch_tx_precursor_10,
output up_ch_enb_10,
@ -381,7 +381,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_11,
output [ 1:0] up_ch_sys_clk_sel_11,
output [ 2:0] up_ch_out_clk_sel_11,
output [ 3:0] up_ch_tx_diffctrl_11,
output [ 4:0] up_ch_tx_diffctrl_11,
output [ 4:0] up_ch_tx_postcursor_11,
output [ 4:0] up_ch_tx_precursor_11,
output up_ch_enb_11,
@ -414,7 +414,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_12,
output [ 1:0] up_ch_sys_clk_sel_12,
output [ 2:0] up_ch_out_clk_sel_12,
output [ 3:0] up_ch_tx_diffctrl_12,
output [ 4:0] up_ch_tx_diffctrl_12,
output [ 4:0] up_ch_tx_postcursor_12,
output [ 4:0] up_ch_tx_precursor_12,
output up_ch_enb_12,
@ -440,7 +440,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_13,
output [ 1:0] up_ch_sys_clk_sel_13,
output [ 2:0] up_ch_out_clk_sel_13,
output [ 3:0] up_ch_tx_diffctrl_13,
output [ 4:0] up_ch_tx_diffctrl_13,
output [ 4:0] up_ch_tx_postcursor_13,
output [ 4:0] up_ch_tx_precursor_13,
output up_ch_enb_13,
@ -466,7 +466,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_14,
output [ 1:0] up_ch_sys_clk_sel_14,
output [ 2:0] up_ch_out_clk_sel_14,
output [ 3:0] up_ch_tx_diffctrl_14,
output [ 4:0] up_ch_tx_diffctrl_14,
output [ 4:0] up_ch_tx_postcursor_14,
output [ 4:0] up_ch_tx_precursor_14,
output up_ch_enb_14,
@ -492,7 +492,7 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_15,
output [ 1:0] up_ch_sys_clk_sel_15,
output [ 2:0] up_ch_out_clk_sel_15,
output [ 3:0] up_ch_tx_diffctrl_15,
output [ 4:0] up_ch_tx_diffctrl_15,
output [ 4:0] up_ch_tx_postcursor_15,
output [ 4:0] up_ch_tx_precursor_15,
output up_ch_enb_15,
@ -605,7 +605,7 @@ module axi_adxcvr #(
wire [ 2:0] up_ch_rate;
wire [ 1:0] up_ch_sys_clk_sel;
wire [ 2:0] up_ch_out_clk_sel;
wire [ 3:0] up_ch_tx_diffctrl;
wire [ 4:0] up_ch_tx_diffctrl;
wire [ 4:0] up_ch_tx_postcursor;
wire [ 4:0] up_ch_tx_precursor;
wire up_ch_pll_locked_0_s;

1
library/xilinx/axi_adxcvr/axi_adxcvr_es.v
View File

@ -93,6 +93,7 @@ module axi_adxcvr_es (
localparam GTXE2 = 2;
localparam GTHE3 = 5;
localparam GTHE4 = 8;
localparam GTYE4 = 9;
// addresses

6
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
View File

@ -77,7 +77,7 @@ module axi_adxcvr_up #(
output [ 2:0] up_ch_rate,
output [ 1:0] up_ch_sys_clk_sel,
output [ 2:0] up_ch_out_clk_sel,
output [ 3:0] up_ch_tx_diffctrl,
output [ 4:0] up_ch_tx_diffctrl,
output [ 4:0] up_ch_tx_postcursor,
output [ 4:0] up_ch_tx_precursor,
output [ 7:0] up_ch_sel,
@ -140,7 +140,7 @@ module axi_adxcvr_up #(
reg [ 2:0] up_rate = RATE;
reg [ 1:0] up_sys_clk_sel = SYS_CLK_SEL;
reg [ 2:0] up_out_clk_sel = OUT_CLK_SEL;
reg [ 3:0] up_tx_diffctrl = TX_DIFFCTRL;
reg [ 4:0] up_tx_diffctrl = TX_DIFFCTRL;
reg [ 4:0] up_tx_postcursor = TX_POSTCURSOR;
reg [ 4:0] up_tx_precursor = TX_PRECURSOR;
reg [ 7:0] up_icm_sel = 'd0;
@ -265,7 +265,7 @@ module axi_adxcvr_up #(
up_out_clk_sel <= up_wdata[2:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h030)) begin
up_tx_diffctrl <= up_wdata[3:0];
up_tx_diffctrl <= up_wdata[4:0];
end
if ((up_wreq == 1'b1) && (up_waddr == 10'h031)) begin
up_tx_postcursor <= up_wdata[4:0];

34
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -38,7 +38,7 @@
module util_adxcvr #(
// gtxe2(2), gthe3(5), gthe4(8)
// gtxe2(2), gthe3(5), gthe4(8), gtye4(9)
parameter integer XCVR_TYPE = 0,
@ -142,7 +142,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_0,
input [ 1:0] up_tx_sys_clk_sel_0,
input [ 2:0] up_tx_out_clk_sel_0,
input [ 3:0] up_tx_diffctrl_0,
input [ 4:0] up_tx_diffctrl_0,
input [ 4:0] up_tx_postcursor_0,
input [ 4:0] up_tx_precursor_0,
input up_tx_enb_0,
@ -201,7 +201,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_1,
input [ 1:0] up_tx_sys_clk_sel_1,
input [ 2:0] up_tx_out_clk_sel_1,
input [ 3:0] up_tx_diffctrl_1,
input [ 4:0] up_tx_diffctrl_1,
input [ 4:0] up_tx_postcursor_1,
input [ 4:0] up_tx_precursor_1,
input up_tx_enb_1,
@ -260,7 +260,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_2,
input [ 1:0] up_tx_sys_clk_sel_2,
input [ 2:0] up_tx_out_clk_sel_2,
input [ 3:0] up_tx_diffctrl_2,
input [ 4:0] up_tx_diffctrl_2,
input [ 4:0] up_tx_postcursor_2,
input [ 4:0] up_tx_precursor_2,
input up_tx_enb_2,
@ -319,7 +319,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_3,
input [ 1:0] up_tx_sys_clk_sel_3,
input [ 2:0] up_tx_out_clk_sel_3,
input [ 3:0] up_tx_diffctrl_3,
input [ 4:0] up_tx_diffctrl_3,
input [ 4:0] up_tx_postcursor_3,
input [ 4:0] up_tx_precursor_3,
input up_tx_enb_3,
@ -386,7 +386,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_4,
input [ 1:0] up_tx_sys_clk_sel_4,
input [ 2:0] up_tx_out_clk_sel_4,
input [ 3:0] up_tx_diffctrl_4,
input [ 4:0] up_tx_diffctrl_4,
input [ 4:0] up_tx_postcursor_4,
input [ 4:0] up_tx_precursor_4,
input up_tx_enb_4,
@ -445,7 +445,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_5,
input [ 1:0] up_tx_sys_clk_sel_5,
input [ 2:0] up_tx_out_clk_sel_5,
input [ 3:0] up_tx_diffctrl_5,
input [ 4:0] up_tx_diffctrl_5,
input [ 4:0] up_tx_postcursor_5,
input [ 4:0] up_tx_precursor_5,
input up_tx_enb_5,
@ -504,7 +504,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_6,
input [ 1:0] up_tx_sys_clk_sel_6,
input [ 2:0] up_tx_out_clk_sel_6,
input [ 3:0] up_tx_diffctrl_6,
input [ 4:0] up_tx_diffctrl_6,
input [ 4:0] up_tx_postcursor_6,
input [ 4:0] up_tx_precursor_6,
input up_tx_enb_6,
@ -563,7 +563,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_7,
input [ 1:0] up_tx_sys_clk_sel_7,
input [ 2:0] up_tx_out_clk_sel_7,
input [ 3:0] up_tx_diffctrl_7,
input [ 4:0] up_tx_diffctrl_7,
input [ 4:0] up_tx_postcursor_7,
input [ 4:0] up_tx_precursor_7,
input up_tx_enb_7,
@ -630,7 +630,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_8,
input [ 1:0] up_tx_sys_clk_sel_8,
input [ 2:0] up_tx_out_clk_sel_8,
input [ 3:0] up_tx_diffctrl_8,
input [ 4:0] up_tx_diffctrl_8,
input [ 4:0] up_tx_postcursor_8,
input [ 4:0] up_tx_precursor_8,
input up_tx_enb_8,
@ -689,7 +689,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_9,
input [ 1:0] up_tx_sys_clk_sel_9,
input [ 2:0] up_tx_out_clk_sel_9,
input [ 3:0] up_tx_diffctrl_9,
input [ 4:0] up_tx_diffctrl_9,
input [ 4:0] up_tx_postcursor_9,
input [ 4:0] up_tx_precursor_9,
input up_tx_enb_9,
@ -748,7 +748,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_10,
input [ 1:0] up_tx_sys_clk_sel_10,
input [ 2:0] up_tx_out_clk_sel_10,
input [ 3:0] up_tx_diffctrl_10,
input [ 4:0] up_tx_diffctrl_10,
input [ 4:0] up_tx_postcursor_10,
input [ 4:0] up_tx_precursor_10,
input up_tx_enb_10,
@ -807,7 +807,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_11,
input [ 1:0] up_tx_sys_clk_sel_11,
input [ 2:0] up_tx_out_clk_sel_11,
input [ 3:0] up_tx_diffctrl_11,
input [ 4:0] up_tx_diffctrl_11,
input [ 4:0] up_tx_postcursor_11,
input [ 4:0] up_tx_precursor_11,
input up_tx_enb_11,
@ -874,7 +874,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_12,
input [ 1:0] up_tx_sys_clk_sel_12,
input [ 2:0] up_tx_out_clk_sel_12,
input [ 3:0] up_tx_diffctrl_12,
input [ 4:0] up_tx_diffctrl_12,
input [ 4:0] up_tx_postcursor_12,
input [ 4:0] up_tx_precursor_12,
input up_tx_enb_12,
@ -933,7 +933,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_13,
input [ 1:0] up_tx_sys_clk_sel_13,
input [ 2:0] up_tx_out_clk_sel_13,
input [ 3:0] up_tx_diffctrl_13,
input [ 4:0] up_tx_diffctrl_13,
input [ 4:0] up_tx_postcursor_13,
input [ 4:0] up_tx_precursor_13,
input up_tx_enb_13,
@ -992,7 +992,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_14,
input [ 1:0] up_tx_sys_clk_sel_14,
input [ 2:0] up_tx_out_clk_sel_14,
input [ 3:0] up_tx_diffctrl_14,
input [ 4:0] up_tx_diffctrl_14,
input [ 4:0] up_tx_postcursor_14,
input [ 4:0] up_tx_precursor_14,
input up_tx_enb_14,
@ -1051,7 +1051,7 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_15,
input [ 1:0] up_tx_sys_clk_sel_15,
input [ 2:0] up_tx_out_clk_sel_15,
input [ 3:0] up_tx_diffctrl_15,
input [ 4:0] up_tx_diffctrl_15,
input [ 4:0] up_tx_postcursor_15,
input [ 4:0] up_tx_precursor_15,
input up_tx_enb_15,

869
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -126,7 +126,7 @@ module util_adxcvr_xch #(
input [ 2:0] up_tx_rate,
input [ 1:0] up_tx_sys_clk_sel,
input [ 2:0] up_tx_out_clk_sel,
input [ 3:0] up_tx_diffctrl,
input [ 4:0] up_tx_diffctrl,
input [ 4:0] up_tx_postcursor,
input [ 4:0] up_tx_precursor,
input up_tx_enb,
@ -139,6 +139,7 @@ module util_adxcvr_xch #(
localparam GTXE2_TRANSCEIVERS = 2;
localparam GTHE3_TRANSCEIVERS = 5;
localparam GTHE4_TRANSCEIVERS = 8;
localparam GTYE4_TRANSCEIVERS = 9;
// internal registers
@ -703,7 +704,7 @@ module util_adxcvr_xch #(
.TXDATA ({32'd0, tx_data}),
.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
.TXDIFFCTRL (up_tx_diffctrl),
.TXDIFFCTRL (up_tx_diffctrl[3:0]),
.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
@ -1437,7 +1438,7 @@ module util_adxcvr_xch #(
.TXDATAEXTENDRSVD (8'h0),
.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
.TXDIFFCTRL (up_tx_diffctrl),
.TXDIFFCTRL (up_tx_diffctrl[3:0]),
.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
@ -2389,6 +2390,868 @@ module util_adxcvr_xch #(
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]};
assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]};
assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
GTYE4_CHANNEL #(
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
.ADAPT_CFG0 (16'b0000000000000000),
.ADAPT_CFG1 (16'b1111101100011100),
.ADAPT_CFG2 (16'b0000000000000000),
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_RXTERMINATION (1'b1),
.A_TXDIFFCTRL (5'b01100),
.A_TXPROGDIVRESET (1'b0),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CDR_SWAP_MODE_EN (1'b0),
.CFOK_PWRSVE_EN (1'b1),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.CH_HSPMUX (16'b0010000000100000),
.CKCAL1_CFG_0 (16'b1100000011000000),
.CKCAL1_CFG_1 (16'b0001000011000000),
.CKCAL1_CFG_2 (16'b0010000000001000),
.CKCAL1_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_0 (16'b1100000011000000),
.CKCAL2_CFG_1 (16'b1000000011000000),
.CKCAL2_CFG_2 (16'b0001000000000000),
.CKCAL2_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_4 (16'b0000000000000000),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0100000000),
.CLK_COR_SEQ_1_3 (10'b0100000000),
.CLK_COR_SEQ_1_4 (10'b0100000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG0 (16'b0000001010110010),
.CPLL_LOCK_CFG (16'b0000000111101000),
.CPLL_REFCLK_DIV (1),
.CTLE3_OCAP_EXT_CTRL (3'b000),
.CTLE3_OCAP_EXT_EN (1'b0),
.DDI_CTRL (2'b00),
.DDI_REALIGN_WAIT (15),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DELAY_ELEC (1'b0),
.DMONITOR_CFG0 (10'b0000000000),
.DMONITOR_CFG1 (8'b00000000),
.ES_CLK_PHASE_SEL (1'b0),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("FALSE"),
.ES_EYE_SCAN_EN ("FALSE"),
.ES_HORZ_OFFSET (12'b000000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER0 (16'b0000000000000000),
.ES_QUALIFIER1 (16'b0000000000000000),
.ES_QUALIFIER2 (16'b0000000000000000),
.ES_QUALIFIER3 (16'b0000000000000000),
.ES_QUALIFIER4 (16'b0000000000000000),
.ES_QUALIFIER5 (16'b0000000000000000),
.ES_QUALIFIER6 (16'b0000000000000000),
.ES_QUALIFIER7 (16'b0000000000000000),
.ES_QUALIFIER8 (16'b0000000000000000),
.ES_QUALIFIER9 (16'b0000000000000000),
.ES_QUAL_MASK0 (16'b0000000000000000),
.ES_QUAL_MASK1 (16'b0000000000000000),
.ES_QUAL_MASK2 (16'b0000000000000000),
.ES_QUAL_MASK3 (16'b0000000000000000),
.ES_QUAL_MASK4 (16'b0000000000000000),
.ES_QUAL_MASK5 (16'b0000000000000000),
.ES_QUAL_MASK6 (16'b0000000000000000),
.ES_QUAL_MASK7 (16'b0000000000000000),
.ES_QUAL_MASK8 (16'b0000000000000000),
.ES_QUAL_MASK9 (16'b0000000000000000),
.ES_SDATA_MASK0 (16'b0000000000000000),
.ES_SDATA_MASK1 (16'b0000000000000000),
.ES_SDATA_MASK2 (16'b0000000000000000),
.ES_SDATA_MASK3 (16'b0000000000000000),
.ES_SDATA_MASK4 (16'b0000000000000000),
.ES_SDATA_MASK5 (16'b0000000000000000),
.ES_SDATA_MASK6 (16'b0000000000000000),
.ES_SDATA_MASK7 (16'b0000000000000000),
.ES_SDATA_MASK8 (16'b0000000000000000),
.ES_SDATA_MASK9 (16'b0000000000000000),
.EYESCAN_VP_RANGE (0),
.EYE_SCAN_SWAP_EN (1'b0),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (5'b00000),
.ISCAN_CK_PH_SEL2 (1'b0),
.LOCAL_MASTER (1'b1),
.LPBK_BIAS_CTRL (4),
.LPBK_EN_RCAL_B (1'b0),
.LPBK_EXT_RCAL (4'b1000),
.LPBK_IND_CTRL0 (5),
.LPBK_IND_CTRL1 (5),
.LPBK_IND_CTRL2 (5),
.LPBK_RG_CTRL (2),
.OOBDIVCTL (2'b00),
.OOB_PWRUP (1'b0),
.PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
.PCI3_PIPE_RX_ELECIDLE (1'b0),
.PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
.PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
.PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
.PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
.PCI3_RX_FIFO_DISABLE (1'b0),
.PCIE3_CLK_COR_EMPTY_THRSH (5'b00000),
.PCIE3_CLK_COR_FULL_THRSH (6'b010000),
.PCIE3_CLK_COR_MAX_LAT (5'b00100),
.PCIE3_CLK_COR_MIN_LAT (5'b00000),
.PCIE3_CLK_COR_THRSH_TIMER (6'b001000),
.PCIE_64B_DYN_CLKSW_DIS ("FALSE"),
.PCIE_BUFG_DIV_CTRL (16'b0011010100000000),
.PCIE_GEN4_64BIT_INT_EN ("FALSE"),
.PCIE_PLL_SEL_MODE_GEN12 (2'b10),
.PCIE_PLL_SEL_MODE_GEN3 (2'b10),
.PCIE_PLL_SEL_MODE_GEN4 (2'b10),
.PCIE_RXPCS_CFG_GEN3 (16'b0000101010100101),
.PCIE_RXPMA_CFG (16'b0010100000001010),
.PCIE_TXPCS_CFG_GEN3 (16'b0010010010100100),
.PCIE_TXPMA_CFG (16'b0010100000001010),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD0 (16'b0000000000000000),
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PREIQ_FREQ_BST (0),
.RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0),
.RCLK_SIPO_INV_EN (1'b0),
.RTX_BUF_CML_CTRL (3'b011),
.RTX_BUF_TERM_CTRL (2'b00),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXCDR_CFG0 (16'b0000000000000011),
.RXCDR_CFG0_GEN3 (16'b0000000000000011),
.RXCDR_CFG1 (16'b0000000000000000),
.RXCDR_CFG1_GEN3 (16'b0000000000000000),
.RXCDR_CFG2 (16'b0000001001101001),
.RXCDR_CFG2_GEN2 (10'b1001101001),
.RXCDR_CFG2_GEN3 (16'b0000001001101001),
.RXCDR_CFG2_GEN4 (16'b0000000101100100),
.RXCDR_CFG3 (16'b0000000000010010),
.RXCDR_CFG3_GEN2 (6'b010010),
.RXCDR_CFG3_GEN3 (16'b0000000000010010),
.RXCDR_CFG3_GEN4 (16'b0000000000010010),
.RXCDR_CFG4 (16'b0101110011110110),
.RXCDR_CFG4_GEN3 (16'b0101110011110110),
.RXCDR_CFG5 (16'b1011010001101011),
.RXCDR_CFG5_GEN3 (16'b0001010001101011),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_LOCK_CFG0 (16'b0010001000000001),
.RXCDR_LOCK_CFG1 (16'b1001111111111111),
.RXCDR_LOCK_CFG2 (15'b000000000000000 ),
.RXCDR_LOCK_CFG3 (16'b0000000000000000),
.RXCDR_LOCK_CFG4 (16'b0000000000000000),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCFOK_CFG0 (16'b0000000000000000),
.RXCFOK_CFG1 (16'b1000000000010101),
.RXCFOK_CFG2 (16'b0000001010101110),
.RXCKCAL1_IQ_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL1_I_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL1_Q_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_DX_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_D_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000000),
.RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000000),
.RXDFELPMRESET_TIME (7'b0001111),
.RXDFELPM_KL_CFG0 (15'b000000000000000 ),
.RXDFELPM_KL_CFG1 (16'b1010000010000010),
.RXDFELPM_KL_CFG2 (16'b0000000100000000),
.RXDFE_CFG0 (16'b0000101000000000),
.RXDFE_CFG1 (16'b0000000000000000),
.RXDFE_GC_CFG0 (16'b0000000000000000),
.RXDFE_GC_CFG1 (16'b1000000000000000),
.RXDFE_GC_CFG2 (16'b1111111111100000),
.RXDFE_H2_CFG0 (16'b0000000000000000),
.RXDFE_H2_CFG1 (16'b0000000000000010),
.RXDFE_H3_CFG0 (16'b0000000000000000),
.RXDFE_H3_CFG1 (16'b1000000000000010),
.RXDFE_H4_CFG0 (16'b0000000000000000),
.RXDFE_H4_CFG1 (16'b1000000000000010),
.RXDFE_H5_CFG0 (16'b0000000000000000),
.RXDFE_H5_CFG1 (16'b1000000000000010),
.RXDFE_H6_CFG0 (16'b0000000000000000),
.RXDFE_H6_CFG1 (16'b1000000000000010),
.RXDFE_H7_CFG0 (16'b0000000000000000),
.RXDFE_H7_CFG1 (16'b1000000000000010),
.RXDFE_H8_CFG0 (16'b0000000000000000),
.RXDFE_H8_CFG1 (16'b1000000000000010),
.RXDFE_H9_CFG0 (16'b0000000000000000),
.RXDFE_H9_CFG1 (16'b1000000000000010),
.RXDFE_HA_CFG0 (16'b0000000000000000),
.RXDFE_HA_CFG1 (16'b1000000000000010),
.RXDFE_HB_CFG0 (16'b0000000000000000),
.RXDFE_HB_CFG1 (16'b1000000000000010),
.RXDFE_HC_CFG0 (16'b0000000000000000),
.RXDFE_HC_CFG1 (16'b1000000000000010),
.RXDFE_HD_CFG0 (16'b0000000000000000),
.RXDFE_HD_CFG1 (16'b1000000000000010),
.RXDFE_HE_CFG0 (16'b0000000000000000),
.RXDFE_HE_CFG1 (16'b1000000000000010),
.RXDFE_HF_CFG0 (16'b0000000000000000),
.RXDFE_HF_CFG1 (16'b1000000000000010),
.RXDFE_KH_CFG0 (16'b1000000000000000),
.RXDFE_KH_CFG1 (16'b1111111000000000),
.RXDFE_KH_CFG2 (16'b0000001000000000),
.RXDFE_KH_CFG3 (16'b0100000100000001),
.RXDFE_OS_CFG0 (16'b0010000000000000),
.RXDFE_OS_CFG1 (16'b1000000000000000),
.RXDFE_UT_CFG0 (16'b0000000000000000),
.RXDFE_UT_CFG1 (16'b0000000000000011),
.RXDFE_UT_CFG2 (16'b0000000000000000),
.RXDFE_VP_CFG0 (16'b0000000000000000),
.RXDFE_VP_CFG1 (16'b0000000000110011),
.RXDLY_CFG (16'b0000000000010000),
.RXDLY_LCFG (16'b0000000000110000),
.RXELECIDLE_CFG ("SIGCFG_4"),
.RXGBOX_FIFO_INIT_RD_ADDR (4),
.RXGEARBOX_EN ("FALSE"),
.RXISCANRESET_TIME (5'b00001),
.RXLPM_CFG (16'b0000000000000000),
.RXLPM_GC_CFG (16'b1111100000000000),
.RXLPM_KH_CFG0 (16'b0000000000000000),
.RXLPM_KH_CFG1 (16'b1010000000000010),
.RXLPM_OS_CFG0 (16'b0000000000000000),
.RXLPM_OS_CFG1 (16'b1000000000000010),
.RXOOB_CFG (9'b000000110),
.RXOOB_CLK_CFG ("PMA"),
.RXOSCALRESET_TIME (5'b00011),
.RXOUT_DIV (RX_OUT_DIV),
.RXPCSRESET_TIME (5'b00011),
.RXPHBEACON_CFG (16'b0000000000000000),
.RXPHDLY_CFG (16'b0010000001110000),
.RXPHSAMP_CFG (16'b0010000100000000),
.RXPHSLIP_CFG (16'b1001100100110011),
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_CFG0 (16'b0000000100000000),
.RXPI_CFG1 (16'b0000000001010100),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
.RXPRBS_LINKACQ_CNT (15),
.RXREFCLKDIV2_SEL (1'b0),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
.RX_AFE_CM_EN (1'b0),
.RX_BIAS_CFG0 (16'b0001001010110000),
.RX_BUFFER_CFG (6'b000000),
.RX_CAPFF_SARC_ENB (1'b0),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (1'b1),
.RX_CLK_SLIP_OVRD (5'b00000),
.RX_CM_BUF_CFG (4'b1010),
.RX_CM_BUF_PD (1'b0),
.RX_CM_SEL (3),
.RX_CM_TRIM (10),
.RX_CTLE_PWR_SAVING (1'b0),
.RX_CTLE_RES_CTRL (4'b0000),
.RX_DATA_WIDTH (40),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DEGEN_CTRL (3'b100),
.RX_DFELPM_CFG0 (10),
.RX_DFELPM_CFG1 (1'b1),
.RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
.RX_DFE_AGC_CFG1 (2),
.RX_DFE_KL_LPM_KH_CFG0 (3),
.RX_DFE_KL_LPM_KH_CFG1 (2),
.RX_DFE_KL_LPM_KL_CFG0 (2'b11),
.RX_DFE_KL_LPM_KL_CFG1 (2),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_DIVRESET_TIME (5'b00001),
.RX_EN_CTLE_RCAL_B (1'b0),
.RX_EN_SUM_RCAL_B (0),
.RX_EYESCAN_VS_CODE (7'b0000000),
.RX_EYESCAN_VS_NEG_DIR (1'b0),
.RX_EYESCAN_VS_RANGE (2'b10),
.RX_EYESCAN_VS_UT_SIGN (1'b0),
.RX_FABINT_USRCLK_FLOP (1'b0),
.RX_I2V_FILTER_EN (1'b1),
.RX_INT_DATAWIDTH (1),
.RX_PMA_POWER_SAVE (1'b0),
.RX_PMA_RSV0 (16'b0000000000101111),
.RX_PROGDIV_CFG (0.0),
.RX_PROGDIV_RATE (16'b0000000000000001),
.RX_RESLOAD_CTRL (4'b0000),
.RX_RESLOAD_OVRD (1'b0),
.RX_SAMPLE_PERIOD (3'b111),
.RX_SIG_VALID_DLY (11),
.RX_SUM_DEGEN_AVTT_OVERITE (0),
.RX_SUM_DFETAPREP_EN (1'b0),
.RX_SUM_IREF_TUNE (4'b0000),
.RX_SUM_PWR_SAVING (0),
.RX_SUM_RES_CTRL (4'b0000),
.RX_SUM_VCMTUNE (4'b0011),
.RX_SUM_VCM_BIAS_TUNE_EN (1'b1),
.RX_SUM_VCM_OVWR (1'b0),
.RX_SUM_VREF_TUNE (3'b100),
.RX_TUNE_AFE_OS (2'b10),
.RX_VREG_CTRL (3'b010),
.RX_VREG_PDB (1'b1),
.RX_WIDEMODE_CDR (2'b00),
.RX_WIDEMODE_CDR_GEN3 (2'b00),
.RX_WIDEMODE_CDR_GEN4 (2'b01),
.RX_XCLK_SEL ("RXDES"),
.RX_XMODE_SEL (1'b1),
.SAMPLE_CLK_PHASE (1'b0),
.SAS_12G_MODE (1'b0),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b100),
.SHOW_REALIGN_COMMA ("TRUE"),
.SIM_MODE ("FAST"),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("Z"),
.SIM_DEVICE ("ULTRASCALE_PLUS"),
.SRSTMODE (1'b0),
.TAPDLY_SET_TX (2'b00),
.TERM_RCAL_CFG (15'b100001000000010),
.TERM_RCAL_OVRD (3'b001),
.TRANS_TIME_RATE (8'b00001110),
.TST_RSV0 (8'b00000000),
.TST_RSV1 (8'b00000000),
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'b1000000000010000),
.TXDLY_LCFG (16'b0000000000110000),
.TXDRV_FREQBAND (0),
.TXFE_CFG0 (16'b0000001111000010),
.TXFE_CFG1 (16'b0110110000000000),
.TXFE_CFG2 (16'b0110110000000000),
.TXFE_CFG3 (16'b0110110000000000),
.TXFIFO_ADDR_CFG ("LOW"),
.TXGBOX_FIFO_INIT_RD_ADDR (4),
.TXGEARBOX_EN ("FALSE"),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00011),
.TXPHDLY_CFG0 (16'b0110000001110000),
.TXPHDLY_CFG1 (16'b0000000000001111),
.TXPH_CFG (16'b0000001100100011),
.TXPH_CFG2 (16'b0000000000000000),
.TXPH_MONITOR_SEL (5'b00000),
.TXPI_CFG0 (16'b0000001100000000),
.TXPI_CFG1 (16'b0001000000000000),
.TXPI_GRAY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_PPM (1'b0),
.TXPI_PPM_CFG (8'b00000000),
.TXPI_SYNFREQ_PPM (3'b001),
.TXPMARESET_TIME (5'b00011),
.TXREFCLKDIV2_SEL (1'b0),
.TXSWBST_BST (1),
.TXSWBST_EN (0),
.TXSWBST_MAG (4),
.TXSYNC_MULTILANE (1'b1),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (1'b1),
.TX_DATA_WIDTH (40),
.TX_DCC_LOOP_RST_CFG (16'b0000000000000100),
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_DEEMPH2 (6'b000000),
.TX_DEEMPH3 (6'b000000),
.TX_DIVRESET_TIME (5'b00001),
.TX_DRIVE_MODE ("DIRECT"),
.TX_EIDLE_ASSERT_DELAY (3'b100),
.TX_EIDLE_DEASSERT_DELAY (3'b011),
.TX_FABINT_USRCLK_FLOP (1'b0),
.TX_FIFO_BYP_EN (1'b0),
.TX_IDLE_DATA_ZERO (1'b0),
.TX_INT_DATAWIDTH (1),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1011000),
.TX_MARGIN_FULL_1 (7'b1010111),
.TX_MARGIN_FULL_2 (7'b1010101),
.TX_MARGIN_FULL_3 (7'b1010011),
.TX_MARGIN_FULL_4 (7'b1010001),
.TX_MARGIN_LOW_0 (7'b1001100),
.TX_MARGIN_LOW_1 (7'b1001011),
.TX_MARGIN_LOW_2 (7'b1001000),
.TX_MARGIN_LOW_3 (7'b1000010),
.TX_MARGIN_LOW_4 (7'b1000000),
.TX_PHICAL_CFG0 (16'b0000000000100000),
.TX_PHICAL_CFG1 (16'b0000000001000000),
.TX_PI_BIASSET (0),
.TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0),
.TX_PMA_RSV0 (16'b0000000000000000),
.TX_PMA_RSV1 (16'b0000000000000000),
.TX_PROGCLK_SEL ("PREPI"),
.TX_PROGDIV_CFG (0.0),
.TX_PROGDIV_RATE (16'b0000000000000001),
.TX_RXDETECT_CFG (14'b00000000110010 ),
.TX_RXDETECT_REF (5),
.TX_SAMPLE_PERIOD (3'b111),
.TX_SW_MEAS (2'b00),
.TX_VREG_CTRL (3'b011),
.TX_VREG_PDB (1'b1),
.TX_VREG_VREFSEL (2'b10),
.TX_XCLK_SEL ("TXOUT"),
.USB_BOTH_BURST_IDLE (1'b0),
.USB_BURSTMAX_U3WAKE (7'b1111111),
.USB_BURSTMIN_U3WAKE (7'b1100011),
.USB_CLK_COR_EQ_EN (1'b0),
.USB_EXT_CNTL (1'b1),
.USB_IDLEMAX_POLLING (10'b1010111011),
.USB_IDLEMIN_POLLING (10'b0100101011),
.USB_LFPSPING_BURST (9'b000000101),
.USB_LFPSPOLLING_BURST (9'b000110001),
.USB_LFPSPOLLING_IDLE_MS (9'b000000100),
.USB_LFPSU1EXIT_BURST (9'b000011101),
.USB_LFPSU2LPEXIT_BURST_MS (9'b001100011),
.USB_LFPSU3WAKE_BURST_MS (9'b111110011),
.USB_LFPS_TPERIOD (4'b0011),
.USB_LFPS_TPERIOD_ACCURATE (1'b1),
.USB_MODE (1'b0),
.USB_PCIE_ERR_REP_DIS (1'b0),
.USB_PING_SATA_MAX_INIT (21),
.USB_PING_SATA_MIN_INIT (12),
.USB_POLL_SATA_MAX_BURST (8),
.USB_POLL_SATA_MIN_BURST (4),
.USB_RAW_ELEC (1'b0),
.USB_RXIDLE_P0_CTRL (1'b1),
.USB_TXIDLE_TUNE_ENABLE (1'b1),
.USB_U1_SATA_MAX_WAKE (7),
.USB_U1_SATA_MIN_WAKE (4),
.USB_U2_SAS_MAX_COM (64),
.USB_U2_SAS_MIN_COM (36),
.USE_PCS_CLK_PHASE_SEL (1'b0),
.Y_ALL_MODE (1'b0))
i_gtye4_channel (
.CDRSTEPDIR (1'b0),
.CDRSTEPSQ (1'b0),
.CDRSTEPSX (1'b0),
.CFGRESET (1'b0),
.CLKRSVD0 (1'b0),
.CLKRSVD1 (1'b0),
.CPLLFREQLOCK (1'b0),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'b1),
.CPLLPD (up_cpll_rst),
.CPLLREFCLKSEL (3'b001),
.CPLLRESET (1'b0),
.DMONFIFORESET (1'b0),
.DMONITORCLK (1'b0),
.DRPADDR (up_addr_int[9:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPEN (up_enb_int),
.DRPRST (1'd0),
.DRPWE (up_wr_int),
.EYESCANRESET (up_es_reset),
.EYESCANTRIGGER (1'b0),
.FREQOS (1'b0),
.GTGREFCLK (1'b0),
.GTNORTHREFCLK0 (1'b0),
.GTNORTHREFCLK1 (1'b0),
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'b0),
.GTRSVD (16'b0000000000000000),
.GTRXRESET (up_rx_rst),
.GTRXRESETSEL (1'b0),
.GTSOUTHREFCLK0 (1'b0),
.GTSOUTHREFCLK1 (1'b0),
.GTTXRESET (up_tx_rst),
.GTTXRESETSEL (1'b0),
.GTYRXN (rx_n),
.GTYRXP (rx_p),
.INCPCTRL (1'b0),
.LOOPBACK (3'b000),
.PCIEEQRXEQADAPTDONE (1'b0),
.PCIERSTIDLE (1'b0),
.PCIERSTTXSYNCSTART (1'b0),
.PCIEUSERRATEDONE (1'b0),
.PCSRSVDIN (16'b0000000000000000),
.QPLL0CLK (qpll2ch_clk),
.QPLL0FREQLOCK (1'b0),
.QPLL0REFCLK (qpll2ch_ref_clk),
.QPLL1CLK (qpll1_clk),
.QPLL1FREQLOCK (1'b0),
.QPLL1REFCLK (qpll1_ref_clk),
.RESETOVRD (1'b0),
.RX8B10BEN (1'b1),
.RXAFECFOKEN (1'b1),
.RXBUFRESET (1'b0),
.RXCDRFREQRESET (1'b0),
.RXCDRHOLD (1'b0),
.RXCDROVRDEN (1'b0),
.RXCDRRESET (1'b0),
.RXCHBONDEN (1'b0),
.RXCHBONDI (5'b00000),
.RXCHBONDLEVEL (3'b000),
.RXCHBONDMASTER (1'b0),
.RXCHBONDSLAVE (1'b0),
.RXCKCALRESET (1'b0),
.RXCKCALSTART (7'b0000000),
.RXCOMMADETEN (1'b1),
.RXDFEAGCHOLD (1'b0),
.RXDFEAGCOVRDEN (1'b0),
.RXDFECFOKFCNUM (4'b1101),
.RXDFECFOKFEN (1'b0),
.RXDFECFOKFPULSE (1'b0),
.RXDFECFOKHOLD (1'b0),
.RXDFECFOKOVREN (1'b0),
.RXDFEKHHOLD (1'b0),
.RXDFEKHOVRDEN (1'b0),
.RXDFELFHOLD (1'b0),
.RXDFELFOVRDEN (1'b0),
.RXDFELPMRESET (1'b0),
.RXDFETAP10HOLD (1'b0),
.RXDFETAP10OVRDEN (1'b0),
.RXDFETAP11HOLD (1'b0),
.RXDFETAP11OVRDEN (1'b0),
.RXDFETAP12HOLD (1'b0),
.RXDFETAP12OVRDEN (1'b0),
.RXDFETAP13HOLD (1'b0),
.RXDFETAP13OVRDEN (1'b0),
.RXDFETAP14HOLD (1'b0),
.RXDFETAP14OVRDEN (1'b0),
.RXDFETAP15HOLD (1'b0),
.RXDFETAP15OVRDEN (1'b0),
.RXDFETAP2HOLD (1'b0),
.RXDFETAP2OVRDEN (1'b0),
.RXDFETAP3HOLD (1'b0),
.RXDFETAP3OVRDEN (1'b0),
.RXDFETAP4HOLD (1'b0),
.RXDFETAP4OVRDEN (1'b0),
.RXDFETAP5HOLD (1'b0),
.RXDFETAP5OVRDEN (1'b0),
.RXDFETAP6HOLD (1'b0),
.RXDFETAP6OVRDEN (1'b0),
.RXDFETAP7HOLD (1'b0),
.RXDFETAP7OVRDEN (1'b0),
.RXDFETAP8HOLD (1'b0),
.RXDFETAP8OVRDEN (1'b0),
.RXDFETAP9HOLD (1'b0),
.RXDFETAP9OVRDEN (1'b0),
.RXDFEUTHOLD (1'b0),
.RXDFEUTOVRDEN (1'b0),
.RXDFEVPHOLD (1'b0),
.RXDFEVPOVRDEN (1'b0),
.RXDFEXYDEN (1'b0),
.RXDLYBYPASS (1'b1),
.RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0),
.RXDLYSRESET (1'b0),
.RXELECIDLEMODE (2'b11),
.RXEQTRAINING (1'b0),
.RXGEARBOXSLIP (1'b0),
.RXLATCLK (1'b0),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMGCHOLD (1'b0),
.RXLPMGCOVRDEN (1'b0),
.RXLPMHFHOLD (1'b0),
.RXLPMHFOVRDEN (1'b0),
.RXLPMLFHOLD (1'b0),
.RXLPMLFKLOVRDEN (1'b0),
.RXLPMOSHOLD (1'b0),
.RXLPMOSOVRDEN (1'b0),
.RXMCOMMAALIGNEN (rx_calign),
.RXMONITORSEL (2'b00),
.RXOOBRESET (1'b0),
.RXOSCALRESET (1'b0),
.RXOSHOLD (1'b0),
.RXOSOVRDEN (1'b0),
.RXOUTCLKSEL (up_rx_out_clk_sel),
.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'b0),
.RXPD (2'b0),
.RXPHALIGN (1'b0),
.RXPHALIGNEN (1'b0),
.RXPHDLYPD (1'b0),
.RXPHDLYRESET (1'b0),
.RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'b0),
.RXPOLARITY (RX_POLARITY),
.RXPRBSCNTRESET (1'b0),
.RXPRBSSEL (4'b0000),
.RXPROGDIVRESET (1'b0),
.RXRATE (rx_rate_m2),
.RXRATEMODE (1'b0),
.RXSLIDE (1'b0),
.RXSLIPOUTCLK (1'b0),
.RXSLIPPMA (1'b0),
.RXSYNCALLIN (1'b0),
.RXSYNCIN (1'b0),
.RXSYNCMODE (1'b0),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXTERMINATION (1'b0),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
.SIGVALIDCLK (1'b0),
.TSTIN (20'b00000000000000000000),
.TX8B10BBYPASS (1'b0),
.TX8B10BEN (1'b1),
.TXCOMINIT (1'b0),
.TXCOMSAS (1'b0),
.TXCOMWAKE (1'b0),
.TXCTRL0 (16'b0000000000000000),
.TXCTRL1 (16'b0000000000000000),
.TXCTRL2 ({4'd0, tx_charisk}),
.TXDATA ({96'd0, tx_data}),
.TXDATAEXTENDRSVD (8'b00000000),
.TXDCCFORCESTART (1'b0),
.TXDCCRESET (1'b0),
.TXDEEMPH (2'b00),
.TXDETECTRX (1'b0),
.TXDIFFCTRL (up_tx_diffctrl),
.TXDLYBYPASS (1'b1),
.TXDLYEN (1'b0),
.TXDLYHOLD (1'b0),
.TXDLYOVRDEN (1'b0),
.TXDLYSRESET (1'b0),
.TXDLYUPDOWN (1'b0),
.TXELECIDLE (1'b0),
.TXHEADER (5'b00000),
.TXINHIBIT (1'b0),
.TXLATCLK (1'b0),
.TXLFPSTRESET (1'b0),
.TXLFPSU2LPEXIT (1'b0),
.TXLFPSU3WAKE (1'b0),
.TXMAINCURSOR (7'b1010000),
.TXMARGIN (3'b000),
.TXMUXDCDEXHOLD (1'b0),
.TXMUXDCDORWREN (1'b0),
.TXONESZEROS (1'b0),
.TXOUTCLKSEL (up_tx_out_clk_sel),
.TXPCSRESET (1'b0),
.TXPD (2'b0),
.TXPDELECIDLEMODE (1'b0),
.TXPHALIGN (1'b0),
.TXPHALIGNEN (1'b0),
.TXPHDLYPD (1'b0),
.TXPHDLYRESET (1'b0),
.TXPHDLYTSTCLK (1'b0),
.TXPHINIT (1'b0),
.TXPHOVRDEN (1'b0),
.TXPIPPMEN (1'b0),
.TXPIPPMOVRDEN (1'b0),
.TXPIPPMPD (1'b0),
.TXPIPPMSEL (1'b0),
.TXPIPPMSTEPSIZE (5'b00000),
.TXPISOPD (1'b0),
.TXPLLCLKSEL (tx_pll_clk_sel_s),
.TXPMARESET (1'b0),
.TXPOLARITY (TX_POLARITY),
.TXPOSTCURSOR (up_tx_postcursor),
.TXPRBSFORCEERR (1'b0),
.TXPRBSSEL (4'b0000),
.TXPRECURSOR (up_tx_precursor),
.TXPROGDIVRESET (up_tx_rst),
.TXRATE (tx_rate_m2),
.TXRATEMODE (1'b0),
.TXSEQUENCE (7'b0000000),
.TXSWING (1'b0),
.TXSYNCALLIN (1'b0),
.TXSYNCIN (1'b0),
.TXSYNCMODE (1'b0),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk),
.BUFGTCE (),
.BUFGTCEMASK (),
.BUFGTDIV (),
.BUFGTRESET (),
.BUFGTRSTMASK (),
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
.CPLLREFCLKLOST (),
.DMONITOROUT (),
.DMONITOROUTCLK (),
.DRPDO (up_rdata_s),
.DRPRDY (up_ready_s),
.EYESCANDATAERROR (),
.GTPOWERGOOD (),
.GTREFCLKMONITOR (),
.GTYTXN (tx_n),
.GTYTXP (tx_p),
.PCIERATEGEN3 (),
.PCIERATEIDLE (),
.PCIERATEQPLLPD (),
.PCIERATEQPLLRESET (),
.PCIESYNCTXSYNCDONE (),
.PCIEUSERGEN3RDY (),
.PCIEUSERPHYSTATUSRST (),
.PCIEUSERRATESTART (),
.PCSRSVDOUT (),
.PHYSTATUS (),
.PINRSRVDAS (),
.POWERPRESENT (),
.RESETEXCEPTION (),
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCDRLOCK (),
.RXCDRPHDONE (),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCHBONDO (),
.RXCKCALDONE (),
.RXCLKCORCNT (),
.RXCOMINITDET (),
.RXCOMMADET (),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
.RXCTRL2 (),
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
.RXDATA ({rx_data_open_s, rx_data}),
.RXDATAEXTENDRSVD (),
.RXDATAVALID (),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXHEADER (),
.RXHEADERVALID (),
.RXLFPSTRESETDET (),
.RXLFPSU2LPEXITDET (),
.RXLFPSU3WAKEDET (),
.RXMONITOROUT (),
.RXOSINTDONE (),
.RXOSINTSTARTED (),
.RXOSINTSTROBEDONE (),
.RXOSINTSTROBESTARTED (),
.RXOUTCLK (rx_out_clk_s),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXPHALIGNDONE (),
.RXPHALIGNERR (),
.RXPMARESETDONE (),
.RXPRBSERR (),
.RXPRBSLOCKED (),
.RXPRGDIVRESETDONE (),
.RXRATEDONE (),
.RXRECCLKOUT (),
.RXRESETDONE (rx_rst_done_s),
.RXSLIDERDY (),
.RXSLIPDONE (),
.RXSLIPOUTCLKRDY (),
.RXSLIPPMARDY (),
.RXSTARTOFSEQ (),
.RXSTATUS (),
.RXSYNCDONE (),
.RXSYNCOUT (),
.RXVALID (),
.TXBUFSTATUS (),
.TXCOMFINISH (),
.TXDCCDONE (),
.TXDLYSRESETDONE (),
.TXOUTCLK (tx_out_clk_s),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXPHALIGNDONE (),
.TXPHINITDONE (),
.TXPMARESETDONE (),
.TXPRGDIVRESETDONE (),
.TXRATEDONE (),
.TXRESETDONE (tx_rst_done_s),
.TXSYNCDONE (),
.TXSYNCOUT ()
);
end
endgenerate
endmodule
// ***************************************************************************

202
library/xilinx/util_adxcvr/util_adxcvr_xcm.v
View File

@ -59,6 +59,7 @@ module util_adxcvr_xcm #(
output qpll2ch_clk,
output qpll2ch_ref_clk,
output qpll2ch_locked,
output qpll1_clk,
output qpll1_ref_clk,
output qpll1_locked,
@ -78,6 +79,7 @@ module util_adxcvr_xcm #(
localparam GTXE2_TRANSCEIVERS = 2;
localparam GTHE3_TRANSCEIVERS = 5;
localparam GTHE4_TRANSCEIVERS = 8;
localparam GTYE4_TRANSCEIVERS = 9;
// internal registers
@ -527,6 +529,206 @@ module util_adxcvr_xcm #(
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
GTYE4_COMMON #(
.AEN_QPLL0_FBDIV (1'b1),
.AEN_QPLL1_FBDIV (1'b1),
.AEN_SDM0TOGGLE (1'b0),
.AEN_SDM1TOGGLE (1'b0),
.A_SDM0TOGGLE (1'b0),
.A_SDM1DATA_HIGH (9'b000000000),
.A_SDM1DATA_LOW (16'b0000000000000000),
.A_SDM1TOGGLE (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000100100100),
.BIAS_CFG3 (16'b0000000001000001),
.BIAS_CFG4 (16'b0000000000010000),
.BIAS_CFG_RSVD (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000000),
.PPF0_CFG (16'b0000100000000000),
.PPF1_CFG (16'b0000011000000000),
.QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (QPLL_CFG0),
.QPLL0_CFG1 (QPLL_CFG1),
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
.QPLL0_CFG2 (QPLL_CFG2),
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
.QPLL0_CFG3 (QPLL_CFG3),
.QPLL0_CFG4 (QPLL_CFG4),
.QPLL0_CP (10'b0011111111),
.QPLL0_CP_G3 (10'b0000001111),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (160),
.QPLL0_INIT_CFG0 (16'b0000001010110010),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_LPF (10'b1101111111),
.QPLL0_LPF_G3 (10'b0111010101),
.QPLL0_PCI_EN (1'b0),
.QPLL0_RATE_SW_USE_DRP (1'b1),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL0_SDM_CFG0 (16'b0000000010000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1CLKOUT_RATE ("HALF"),
.QPLL1_CFG0 (QPLL_CFG0),
.QPLL1_CFG1 (QPLL_CFG1),
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
.QPLL1_CFG2 (QPLL_CFG2),
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
.QPLL1_CFG3 (QPLL_CFG3),
.QPLL1_CFG4 (QPLL_CFG4),
.QPLL1_CP (10'b0011111111),
.QPLL1_CP_G3 (10'b0001111111),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_INIT_CFG0 (16'b0000001010110010),
.QPLL1_INIT_CFG1 (8'b00000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_LPF (10'b1000011111),
.QPLL1_LPF_G3 (10'b0111010100),
.QPLL1_PCI_EN (1'b0),
.QPLL1_RATE_SW_USE_DRP (1'b1),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_SDM_CFG0 (16'b0000000010000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.SARC_ENB (1'b0),
.SARC_SEL (1'b0),
.SDM0INITSEED0_0 (16'b0000000100010001),
.SDM0INITSEED0_1 (9'b000010001),
.SDM1INITSEED0_0 (16'b0000000100010001),
.SDM1INITSEED0_1 (9'b000010001),
.SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_DEVICE ("ULTRASCALE_PLUS"),
.UB_CFG0 (16'b0000000000000000),
.UB_CFG1 (16'b0000000000000000),
.UB_CFG2 (16'b0000000000000000),
.UB_CFG3 (16'b0000000000000000),
.UB_CFG4 (16'b0000000000000000),
.UB_CFG5 (16'b0000010000000000),
.UB_CFG6 (16'b0000000000000000))
i_gtye4_common (
.BGBYPASSB (1'b1),
.BGMONITORENB (1'b1),
.BGPDB (1'b1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'b1),
.DRPADDR ({4'd0, up_addr_int}),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPEN (up_enb_int),
.DRPWE (up_wr_int),
.GTGREFCLK0 (1'b0),
.GTGREFCLK1 (1'b0),
.GTNORTHREFCLK00 (1'b0),
.GTNORTHREFCLK01 (1'b0),
.GTNORTHREFCLK10 (1'b0),
.GTNORTHREFCLK11 (1'b0),
.GTREFCLK00 (qpll_ref_clk),
.GTREFCLK01 (qpll_ref_clk),
.GTREFCLK10 (1'b0),
.GTREFCLK11 (1'b0),
.GTSOUTHREFCLK00 (1'b0),
.GTSOUTHREFCLK01 (1'b0),
.GTSOUTHREFCLK10 (1'b0),
.GTSOUTHREFCLK11 (1'b0),
.PCIERATEQPLL0 (3'b0),
.PCIERATEQPLL1 (3'b0),
.PMARSVD0 (8'b0),
.PMARSVD1 (8'b0),
.QPLL0CLKRSVD0 (1'b0),
.QPLL0CLKRSVD1 (1'b0),
.QPLL0FBDIV (8'b0),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'b1),
.QPLL0PD (qpll_sel),
.QPLL0REFCLKSEL (3'b1),
.QPLL0RESET (up_qpll_rst),
.QPLL1CLKRSVD0 (1'b0),
.QPLL1CLKRSVD1 (1'b0),
.QPLL1FBDIV (8'b0),
.QPLL1LOCKDETCLK (up_clk),
.QPLL1LOCKEN (1'b1),
.QPLL1PD (~qpll_sel),
.QPLL1REFCLKSEL (3'b1),
.QPLL1RESET (up_qpll_rst),
.QPLLRSVD1 (8'b0),
.QPLLRSVD2 (5'b0),
.QPLLRSVD3 (5'b0),
.QPLLRSVD4 (8'b0),
.RCALENB (1'b1),
.SDM0DATA (25'b0),
.SDM0RESET (1'b0),
.SDM0TOGGLE (1'b0),
.SDM0WIDTH (2'b0),
.SDM1DATA (25'b0),
.SDM1RESET (1'b0),
.SDM1TOGGLE (1'b0),
.SDM1WIDTH (2'b0),
.UBCFGSTREAMEN (1'b0),
.UBDO (16'b0),
.UBDRDY (1'b0),
.UBENABLE (1'b0),
.UBGPI (2'b0),
.UBINTR (2'b0),
.UBIOLMBRST (1'b0),
.UBMBRST (1'b0),
.UBMDMCAPTURE (1'b0),
.UBMDMDBGRST (1'b0),
.UBMDMDBGUPDATE (1'b0),
.UBMDMREGEN (4'b0),
.UBMDMSHIFT (1'b0),
.UBMDMSYSRST (1'b0),
.UBMDMTCK (1'b0),
.UBMDMTDI (1'b0),
.DRPDO ( up_rdata_s),
.DRPRDY ( up_ready_s),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLL0FBCLKLOST (),
.QPLL0LOCK ( qpll2ch_locked),
.QPLL0OUTCLK ( qpll2ch_clk),
.QPLL0OUTREFCLK ( qpll2ch_ref_clk),
.QPLL0REFCLKLOST (),
.QPLL1FBCLKLOST (),
.QPLL1LOCK ( qpll1_locked),
.QPLL1OUTCLK ( qpll1_clk),
.QPLL1OUTREFCLK ( qpll1_ref_clk),
.QPLL1REFCLKLOST (),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0SEL (),
.RXRECCLK1SEL (),
.SDM0FINALOUT (),
.SDM0TESTDATA (),
.SDM1FINALOUT (),
.SDM1TESTDATA (),
.UBDADDR (),
.UBDEN (),
.UBDI (),
.UBDWE (),
.UBMDMTDO (),
.UBRSVDOUT (),
.UBTXUART ());
end
endgenerate
endmodule
// ***************************************************************************