axi_streaming_dma_tx_fifo: Fix drain logic

At the moment the drain signal is always asserted when the controller is
enabled. This breaks backpressure and data is lost. The drain signal should
only be asserted when the controller gets disabled until the last beat of
the current DMA transfer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/common/axi_streaming_dma_tx_fifo.vhd

@@ -97,7 +97,9 @@ begin
 			else
 				if s_axis_tlast = '1' then
 					drain_dma <= False;
-				elsif enable_d1 and enable then
+				elsif not enable_d1 and enable then
+					drain_dma <= False;
+				elsif enable_d1 and not enable then
 					drain_dma <= True;
 				end if;
 				enable_d1 := enable;