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axi_streaming_dma_tx_fifo: Fix drain logic 

At the moment the drain signal is always asserted when the controller is
enabled. This breaks backpressure and data is lost. The drain signal should
only be asserted when the controller gets disabled until the last beat of
the current DMA transfer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-14 15:45:41 +02:00
parent 38f495b2cf
commit 42ff5d4f80
1 changed files with 3 additions and 1 deletions
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4
library/common/axi_streaming_dma_tx_fifo.vhd
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@ -97,7 +97,9 @@ begin
else else
if s_axis_tlast = '1' then if s_axis_tlast = '1' then
drain_dma <= False; drain_dma <= False;
elsif enable_d1 and enable then elsif not enable_d1 and enable then
drain_dma <= False;
elsif enable_d1 and not enable then
drain_dma <= True; drain_dma <= True;
end if; end if;
enable_d1 := enable; enable_d1 := enable;