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ad_dds: Update for CORDIC algorithm integration 

Add parameters:
  - to select the sine generator (polynomial/CORDIC)
  - to select the CORDIC data width(default 16)
Suppress the warnings generated when the DDS is disabled.
main
AndreiGrozav 2018-02-07 13:48:03 +02:00 committed by AndreiGrozav
parent 4c32b47f6a
commit 4362c35125
1 changed files with 40 additions and 25 deletions
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65
library/common/ad_dds.v
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@ -39,8 +39,9 @@ module ad_dds #(
// data path disable // data path disable
parameter DISABLE = 0) ( parameter DISABLE = 0,
parameter DDS_TYPE = 1,
parameter CORDIC_DW = 14) (
// interface // interface
input clk, input clk,
@ -65,35 +66,49 @@ module ad_dds #(
// disable // disable
assign dds_data = (DISABLE == 1) ? 16'd0 : dds_data_out; generate
if (DISABLE == 1) begin
assign dds_data = 16'd0;
end else begin
// dds channel output assign dds_data = dds_data_out;
always @(posedge clk) begin // dds channel output
dds_data_int <= dds_data_0_s + dds_data_1_s;
dds_data_out[15:15] <= dds_data_int[15] ^ dds_format;
dds_data_out[14: 0] <= dds_data_int[14:0];
end
always @(posedge clk) begin always @(posedge clk) begin
dds_scale_0_d <= dds_scale_0; dds_data_int <= dds_data_0_s + dds_data_1_s;
dds_scale_1_d <= dds_scale_1; dds_data_out[15:15] <= dds_data_int[15] ^ dds_format;
end dds_data_out[14: 0] <= dds_data_int[14:0];
// dds-1 end
ad_dds_1 i_dds_1_0 ( always @(posedge clk) begin
.clk (clk), dds_scale_0_d <= dds_scale_0;
.angle (dds_phase_0), dds_scale_1_d <= dds_scale_1;
.scale (dds_scale_0_d), end
.dds_data (dds_data_0_s));
// dds-2 // dds-1
ad_dds_1 i_dds_1_1 ( ad_dds_1 #(
.clk (clk), .CORDIC_DW(CORDIC_DW),
.angle (dds_phase_1), .DDS_TYPE(DDS_TYPE))
.scale (dds_scale_1_d), i_dds_1_0 (
.dds_data (dds_data_1_s)); .clk (clk),
.angle (dds_phase_0),
.scale (dds_scale_0_d),
.dds_data (dds_data_0_s));
// dds-2
ad_dds_1 #(
.CORDIC_DW(CORDIC_DW),
.DDS_TYPE(DDS_TYPE))
i_dds_1_1 (
.clk (clk),
.angle (dds_phase_1),
.scale (dds_scale_1_d),
.dds_data (dds_data_1_s));
end
endgenerate
endmodule endmodule