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fmcomms7: asymmetric no of lanes

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Rejeesh Kutty 2014-11-11 08:53:31 -05:00
parent b96a8d01c3
commit 439cbecf7c
1 changed files with 2 additions and 2 deletions
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projects/fmcomms7/zc706/system_constr.xdc
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@ -102,6 +102,6 @@ set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports hmc922_b
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcomms7_gt_tx_clk]
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcomms7_gt_rx_clk]