From 43e03ca6f7dda8140cf7cfbff903975521f2d640 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 16 Feb 2016 14:50:23 +0200
Subject: [PATCH] arradio: Updated project

- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
---
 projects/arradio/c5soc/system_bd.qsys      |  59 +++---
 projects/arradio/c5soc/system_project.tcl  |   2 +-
 projects/arradio/common/arradio_bd.qsys    | 120 ++++++-------
 projects/common/c5soc/c5soc_system_bd.qsys | 197 +++++++++++----------
 4 files changed, 199 insertions(+), 179 deletions(-)

diff --git a/projects/arradio/c5soc/system_bd.qsys b/projects/arradio/c5soc/system_bd.qsys
index 43627164e..ec86e336c 100644
--- a/projects/arradio/c5soc/system_bd.qsys
+++ b/projects/arradio/c5soc/system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
    element arradio
    {
       datum _sortIndex
@@ -49,6 +41,14 @@
          type = "String";
       }
    }
+   element arradio.gpio_s1
+   {
+      datum baseAddress
+      {
+         value = "36864";
+         type = "String";
+      }
+   }
    element arradio.spi_ad9361_spi_control_port
    {
       datum baseAddress
@@ -233,14 +233,14 @@
   <parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
   <parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
   <parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
-  <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
+  <parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
   <parameter
      name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
      value="AddressWidth = 18" />
   <parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
   <parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
  </module>
- <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
+ <module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
   <parameter name="clockFrequency" value="50000000" />
   <parameter name="clockFrequencyKnown" value="true" />
   <parameter name="inputClockFrequency" value="0" />
@@ -248,7 +248,7 @@
  </module>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="arradio.axi_dmac_adc_m_dest_axi"
    end="c5soc.sys_mem_interconnect_axi0_s0">
   <parameter name="arbitrationPriority" value="1" />
@@ -257,7 +257,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="arradio.axi_dmac_dac_m_src_axi"
    end="c5soc.sys_mem_interconnect_axi1_s0">
   <parameter name="arbitrationPriority" value="1" />
@@ -266,7 +266,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="c5soc.sys_cpu_interconnect_m0"
    end="arradio.axi_ad9361_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -275,7 +275,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="c5soc.sys_cpu_interconnect_m0"
    end="arradio.axi_dmac_adc_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -284,7 +284,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="c5soc.sys_cpu_interconnect_m0"
    end="arradio.axi_dmac_dac_s_axi">
   <parameter name="arbitrationPriority" value="1" />
@@ -293,54 +293,63 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
+   start="c5soc.sys_cpu_interconnect_m0"
+   end="arradio.gpio_s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x9000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="15.1"
    start="c5soc.sys_cpu_interconnect_m0"
    end="arradio.spi_ad9361_spi_control_port">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x8000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection kind="clock" version="15.0" start="sys_clk.clk" end="c5soc.sys_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.clk" end="arradio.sys_clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.clk" end="c5soc.sys_clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.clk" end="arradio.sys_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="c5soc.mem_clk"
    end="arradio.mem_clk" />
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="c5soc.sys_intr"
    end="arradio.axi_dmac_adc_intr">
   <parameter name="irqNumber" value="2" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="c5soc.sys_intr"
    end="arradio.axi_dmac_dac_intr">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="c5soc.sys_intr"
    end="arradio.spi_ad9361_irq">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk_reset"
    end="c5soc.sys_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_clk.clk_reset"
    end="arradio.sys_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="c5soc.mem_rst"
    end="arradio.mem_rst" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
diff --git a/projects/arradio/c5soc/system_project.tcl b/projects/arradio/c5soc/system_project.tcl
index a800bbc31..a00f71e25 100644
--- a/projects/arradio/c5soc/system_project.tcl
+++ b/projects/arradio/c5soc/system_project.tcl
@@ -5,7 +5,7 @@ source ../../scripts/adi_env.tcl
 project_new arradio_c5soc -overwrite
 
 source "../../common/c5soc/c5soc_system_assign.tcl"
-set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/c5soc;../../../library/**/*"
+set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
 set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
 set_global_assignment -name QSYS_FILE system_bd.qsys
 
diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys
index 65720e1a2..ba5d0bed4 100755
--- a/projects/arradio/common/arradio_bd.qsys
+++ b/projects/arradio/common/arradio_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
    element ad9361_clk_bridge
    {
       datum _sortIndex
@@ -86,6 +78,14 @@
          type = "String";
       }
    }
+   element arradio_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
    element axi_ad9361
    {
       datum _sortIndex
@@ -330,7 +330,7 @@
  <module
    name="ad9361_clk_bridge"
    kind="altera_clock_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
@@ -359,7 +359,7 @@
   <parameter name="DMA_TYPE_SRC" value="2" />
   <parameter name="FIFO_SIZE" value="4" />
   <parameter name="ID" value="0" />
-  <parameter name="SYNC_TRANSFER_START" value="0" />
+  <parameter name="SYNC_TRANSFER_START" value="1" />
  </module>
  <module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
   <parameter name="ASYNC_CLK_DEST_REQ" value="1" />
@@ -382,7 +382,7 @@
   <parameter name="CHANNEL_DATA_WIDTH" value="16" />
   <parameter name="NUM_OF_CHANNELS" value="4" />
  </module>
- <module name="gpio" kind="altera_avalon_pio" version="15.0" enabled="1">
+ <module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
   <parameter name="bitModifyingOutReg" value="false" />
   <parameter name="captureEdge" value="false" />
@@ -396,19 +396,19 @@
   <parameter name="simDrivenValue" value="0" />
   <parameter name="width" value="5" />
  </module>
- <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="spi_ad9361" kind="altera_avalon_spi" version="15.0" enabled="1">
+ <module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
   <parameter name="avalonSpec" value="2.0" />
   <parameter name="clockPhase" value="0" />
   <parameter name="clockPolarity" value="1" />
@@ -424,84 +424,82 @@
   <parameter name="targetClockRate" value="50000000" />
   <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
  </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.if_l_clk"
    end="adc_pack.if_adc_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.if_l_clk"
    end="dac_upack.if_dac_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.if_l_clk"
    end="axi_dmac_dac.if_fifo_rd_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.if_l_clk"
    end="axi_dmac_adc.if_fifo_wr_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.if_l_clk"
    end="ad9361_clk_bridge.in_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="spi_ad9361.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
- <connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="gpio.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9361.delay_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_dmac_adc.m_dest_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="mem_clk.out_clk"
    end="axi_dmac_dac.m_src_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_ad9361.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_dmac_adc.s_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="axi_dmac_dac.s_axi_clock" />
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="dac_upack.fifo_ch_0"
    end="axi_ad9361.fifo_ch_0_out">
   <parameter name="endPort" value="" />
@@ -512,7 +510,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.fifo_ch_0_in"
    end="adc_pack.fifo_ch_0">
   <parameter name="endPort" value="" />
@@ -523,7 +521,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.fifo_ch_1_in"
    end="adc_pack.fifo_ch_1">
   <parameter name="endPort" value="" />
@@ -534,7 +532,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.fifo_ch_1_out"
    end="dac_upack.fifo_ch_1">
   <parameter name="endPort" value="" />
@@ -545,7 +543,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.fifo_ch_2_in"
    end="adc_pack.fifo_ch_2">
   <parameter name="endPort" value="" />
@@ -556,7 +554,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.fifo_ch_2_out"
    end="dac_upack.fifo_ch_2">
   <parameter name="endPort" value="" />
@@ -567,7 +565,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.fifo_ch_3_in"
    end="adc_pack.fifo_ch_3">
   <parameter name="endPort" value="" />
@@ -578,7 +576,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.fifo_ch_3_out"
    end="dac_upack.fifo_ch_3">
   <parameter name="endPort" value="" />
@@ -589,7 +587,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="adc_pack.if_adc_data"
    end="axi_dmac_adc.if_fifo_wr_din">
   <parameter name="endPort" value="" />
@@ -600,7 +598,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="adc_pack.if_adc_sync"
    end="axi_dmac_adc.if_fifo_wr_sync">
   <parameter name="endPort" value="" />
@@ -611,7 +609,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="adc_pack.if_adc_valid"
    end="axi_dmac_adc.if_fifo_wr_en">
   <parameter name="endPort" value="" />
@@ -622,7 +620,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="dac_upack.if_dac_data"
    end="axi_dmac_dac.if_fifo_rd_dout">
   <parameter name="endPort" value="" />
@@ -633,7 +631,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="dac_upack.if_dma_xfer_in"
    end="axi_dmac_dac.if_fifo_rd_xfer_req">
   <parameter name="endPort" value="" />
@@ -644,7 +642,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_dmac_dac.if_fifo_rd_en"
    end="dac_upack.if_dac_valid">
   <parameter name="endPort" value="" />
@@ -655,7 +653,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_dmac_dac.if_fifo_rd_underflow"
    end="axi_ad9361.if_dac_dunf">
   <parameter name="endPort" value="" />
@@ -666,7 +664,7 @@
  </connection>
  <connection
    kind="conduit"
-   version="15.0"
+   version="15.1"
    start="axi_dmac_adc.if_fifo_wr_overflow"
    end="axi_ad9361.if_adc_dovf">
   <parameter name="endPort" value="" />
@@ -677,52 +675,52 @@
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="axi_ad9361.if_rst"
    end="adc_pack.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="adc_pack.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="adc_pack.if_adc_rst" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_dmac_adc.m_dest_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="mem_rst.out_reset"
    end="axi_dmac_dac.m_src_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="spi_ad9361.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="gpio.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_ad9361.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_dmac_adc.s_axi_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="axi_dmac_dac.s_axi_reset" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
diff --git a/projects/common/c5soc/c5soc_system_bd.qsys b/projects/common/c5soc/c5soc_system_bd.qsys
index e3b27f495..dab5f0d2f 100644
--- a/projects/common/c5soc/c5soc_system_bd.qsys
+++ b/projects/common/c5soc/c5soc_system_bd.qsys
@@ -9,14 +9,6 @@
    categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
-   element $${FILENAME}
-   {
-      datum _originalDeviceFamily
-      {
-         value = "Cyclone V";
-         type = "String";
-      }
-   }
    element mem_clk
    {
       datum _sortIndex
@@ -24,6 +16,11 @@
          value = "13";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
    }
    element mem_rst
    {
@@ -42,7 +39,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -53,6 +50,11 @@
          value = "10";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
    }
    element sys_cpu_interconnect.s0
    {
@@ -71,7 +73,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -105,7 +107,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -126,7 +128,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -152,7 +154,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -179,6 +181,11 @@
          value = "11";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
    }
    element sys_mem_interconnect_axi1
    {
@@ -187,6 +194,11 @@
          value = "12";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
    }
    element sys_rst
    {
@@ -195,6 +207,11 @@
          value = "1";
          type = "int";
       }
+      datum sopceditor_expanded
+      {
+         value = "0";
+         type = "boolean";
+      }
    }
    element system_bd
    {
@@ -301,7 +318,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -314,7 +331,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -335,7 +352,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -348,7 +365,7 @@
       }
       datum sopceditor_expanded
       {
-         value = "1";
+         value = "0";
          type = "boolean";
       }
    }
@@ -443,19 +460,19 @@
    internal="vga_pixel_clock_bridge.out_clk"
    type="clock"
    dir="start" />
- <module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="80000000" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="80000000" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
- <module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
+ <module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="0" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
@@ -463,7 +480,7 @@
  <module
    name="sys_cpu_interconnect"
    kind="altera_axi_bridge"
-   version="1.0"
+   version="15.1"
    enabled="1">
   <parameter name="ADDR_WIDTH" value="20" />
   <parameter name="AXI_VERSION" value="AXI3" />
@@ -529,7 +546,7 @@
   <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
   <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
  </module>
- <module name="sys_gpio" kind="altera_avalon_pio" version="15.0" enabled="1">
+ <module name="sys_gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="true" />
   <parameter name="bitModifyingOutReg" value="false" />
   <parameter name="captureEdge" value="true" />
@@ -543,7 +560,7 @@
   <parameter name="simDrivenValue" value="0" />
   <parameter name="width" value="32" />
  </module>
- <module name="sys_hps" kind="altera_hps" version="15.0" enabled="1">
+ <module name="sys_hps" kind="altera_hps" version="15.1" enabled="1">
   <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
   <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
   <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
@@ -891,6 +908,7 @@
   <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
   <parameter name="S2FCLK_USER1CLK_Enable" value="false" />
   <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" />
+  <parameter name="S2FCLK_USER2CLK" value="4" />
   <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
   <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" />
   <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
@@ -1047,6 +1065,7 @@
   <parameter name="periph_pll_n" value="1" />
   <parameter name="periph_pll_source" value="0" />
   <parameter name="qspi_clk_source" value="1" />
+  <parameter name="quartus_ini_hps_emif_pll" value="false" />
   <parameter
      name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
      value="false" />
@@ -1072,7 +1091,7 @@
  <module
    name="sys_id"
    kind="altera_avalon_sysid_qsys"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
   <parameter name="id" value="-1395322110" />
@@ -1080,7 +1099,7 @@
  <module
    name="sys_int_mem"
    kind="altera_avalon_onchip_memory2"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="allowInSystemMemoryContentEditor" value="false" />
   <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
@@ -1088,7 +1107,7 @@
   <parameter name="copyInitFile" value="false" />
   <parameter name="dataWidth" value="64" />
   <parameter name="deviceFamily" value="Cyclone V" />
-  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
   <parameter name="dualPort" value="false" />
   <parameter name="ecc_enabled" value="false" />
   <parameter name="initMemContent" value="true" />
@@ -1106,7 +1125,7 @@
   <parameter name="useShallowMemBlocks" value="false" />
   <parameter name="writable" value="true" />
  </module>
- <module name="sys_intr" kind="altera_irq_bridge" version="15.0" enabled="1">
+ <module name="sys_intr" kind="altera_irq_bridge" version="15.1" enabled="1">
   <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
   <parameter name="AUTO_RECEIVER_IRQ_INTERRUPTS_USED" value="0" />
@@ -1116,7 +1135,7 @@
  <module
    name="sys_mem_interconnect_axi0"
    kind="altera_axi_bridge"
-   version="1.0"
+   version="15.1"
    enabled="1">
   <parameter name="ADDR_WIDTH" value="32" />
   <parameter name="AXI_VERSION" value="AXI3" />
@@ -1185,7 +1204,7 @@
  <module
    name="sys_mem_interconnect_axi1"
    kind="altera_axi_bridge"
-   version="1.0"
+   version="15.1"
    enabled="1">
   <parameter name="ADDR_WIDTH" value="32" />
   <parameter name="AXI_VERSION" value="AXI3" />
@@ -1251,11 +1270,11 @@
   <parameter name="WRITE_ISSUING_CAPABILITY" value="16" />
   <parameter name="WRITE_RESP_USER_WIDTH" value="64" />
  </module>
- <module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
+ <module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
   <parameter name="ACTIVE_LOW_RESET" value="0" />
-  <parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
   <parameter name="NUM_RESET_OUTPUTS" value="1" />
-  <parameter name="SYNCHRONOUS_EDGES" value="deassert" />
+  <parameter name="SYNCHRONOUS_EDGES" value="none" />
   <parameter name="USE_RESET_REQUEST" value="0" />
  </module>
  <module
@@ -1315,13 +1334,13 @@
  <module
    name="vga_pixel_clock_bridge"
    kind="altera_clock_bridge"
-   version="15.0"
+   version="15.1"
    enabled="1">
   <parameter name="DERIVED_CLOCK_RATE" value="85500000" />
   <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
   <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
  </module>
- <module name="vga_pll" kind="altera_pll" version="15.0" enabled="1">
+ <module name="vga_pll" kind="altera_pll" version="15.1" enabled="1">
   <parameter name="debug_print_output" value="false" />
   <parameter name="debug_use_rbc_taf_method" value="false" />
   <parameter name="device" value="5CSXFC6D6F31C8ES" />
@@ -1526,7 +1545,7 @@
  </module>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="vga_frame_reader.avalon_master"
    end="sys_hps.f2h_sdram0_data">
   <parameter name="arbitrationPriority" value="1" />
@@ -1535,7 +1554,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_axi_master"
    end="sys_int_mem.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -1544,7 +1563,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_lw_axi_master"
    end="vga_frame_reader.avalon_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -1553,7 +1572,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_lw_axi_master"
    end="sys_id.control_slave">
   <parameter name="arbitrationPriority" value="1" />
@@ -1562,7 +1581,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_lw_axi_master"
    end="sys_cpu_interconnect.s0">
   <parameter name="arbitrationPriority" value="1" />
@@ -1571,7 +1590,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_lw_axi_master"
    end="sys_gpio.s1">
   <parameter name="arbitrationPriority" value="1" />
@@ -1580,7 +1599,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_mem_interconnect_axi0.m0"
    end="sys_hps.f2h_sdram1_data">
   <parameter name="arbitrationPriority" value="1" />
@@ -1589,7 +1608,7 @@
  </connection>
  <connection
    kind="avalon"
-   version="15.0"
+   version="15.1"
    start="sys_mem_interconnect_axi1.m0"
    end="sys_hps.f2h_sdram2_data">
   <parameter name="arbitrationPriority" value="1" />
@@ -1598,234 +1617,228 @@
  </connection>
  <connection
    kind="avalon_streaming"
-   version="15.0"
+   version="15.1"
    start="vga_frame_reader.avalon_streaming_source"
    end="vga_clock_video_output.din" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_user0_clock"
    end="sys_mem_interconnect_axi0.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_user0_clock"
    end="sys_mem_interconnect_axi1.clk" />
  <connection
    kind="clock"
-   version="15.0"
-   start="sys_hps.h2f_user0_clock"
-   end="mem_rst.clk" />
- <connection
-   kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_user0_clock"
    end="sys_hps.f2h_sdram1_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_user0_clock"
    end="sys_hps.f2h_sdram2_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_hps.h2f_user0_clock"
    end="mem_clk.in_clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_id.clk" />
+ <connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_id.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_gpio.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_cpu_interconnect.clk" />
- <connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_intr.clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_int_mem.clk1" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="vga_frame_reader.clock_master" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_hps.f2h_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_hps.f2h_sdram0_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_hps.h2f_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="sys_hps.h2f_lw_axi_clock" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="sys_clk.out_clk"
    end="vga_pll.refclk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="vga_pll.outclk0"
    end="vga_frame_reader.clock_reset" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="vga_pll.outclk0"
    end="vga_pixel_clock_bridge.in_clk" />
  <connection
    kind="clock"
-   version="15.0"
+   version="15.1"
    start="vga_pll.outclk0"
    end="vga_clock_video_output.is_clk_rst" />
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="vga_frame_reader.interrupt_sender">
   <parameter name="irqNumber" value="4" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_gpio.irq">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender0_irq">
   <parameter name="irqNumber" value="1" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender1_irq">
   <parameter name="irqNumber" value="2" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender2_irq">
   <parameter name="irqNumber" value="3" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender3_irq">
   <parameter name="irqNumber" value="5" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender4_irq">
   <parameter name="irqNumber" value="6" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender5_irq">
   <parameter name="irqNumber" value="7" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender6_irq">
   <parameter name="irqNumber" value="8" />
  </connection>
  <connection
    kind="interrupt"
-   version="15.0"
+   version="15.1"
    start="sys_hps.f2h_irq0"
    end="sys_intr.sender7_irq">
   <parameter name="irqNumber" value="9" />
  </connection>
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_cpu_interconnect.clk_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_mem_interconnect_axi0.clk_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_mem_interconnect_axi1.clk_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_intr.clk_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="vga_frame_reader.clock_master_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="vga_frame_reader.clock_reset_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="mem_rst.in_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="vga_clock_video_output.is_clk_rst_reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_id.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_gpio.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="vga_pll.reset" />
  <connection
    kind="reset"
-   version="15.0"
+   version="15.1"
    start="sys_rst.out_reset"
    end="sys_int_mem.reset1" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />