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arradio: Updated project 

- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
main
Adrian Costina 2016-02-16 14:50:23 +02:00
parent 61f9f72a75
commit 43e03ca6f7
4 changed files with 199 additions and 179 deletions
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59
projects/arradio/c5soc/system_bd.qsys
View File

@ -9,14 +9,6 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element arradio
{
datum _sortIndex
@ -49,6 +41,14 @@
type = "String";
}
}
element arradio.gpio_s1
{
datum baseAddress
{
value = "36864";
type = "String";
}
}
element arradio.spi_ad9361_spi_control_port
{
datum baseAddress
@ -233,14 +233,14 @@
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="3" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="3" />
<parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
<parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
<parameter
name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
value="AddressWidth = 18" />
<parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
</module>
<module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
@ -248,7 +248,7 @@
</module>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="arradio.axi_dmac_adc_m_dest_axi"
end="c5soc.sys_mem_interconnect_axi0_s0">
<parameter name="arbitrationPriority" value="1" />
@ -257,7 +257,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="arradio.axi_dmac_dac_m_src_axi"
end="c5soc.sys_mem_interconnect_axi1_s0">
<parameter name="arbitrationPriority" value="1" />
@ -266,7 +266,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="c5soc.sys_cpu_interconnect_m0"
end="arradio.axi_ad9361_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -275,7 +275,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="c5soc.sys_cpu_interconnect_m0"
end="arradio.axi_dmac_adc_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -284,7 +284,7 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="c5soc.sys_cpu_interconnect_m0"
end="arradio.axi_dmac_dac_s_axi">
<parameter name="arbitrationPriority" value="1" />
@ -293,54 +293,63 @@
</connection>
<connection
kind="avalon"
version="15.0"
version="15.1"
start="c5soc.sys_cpu_interconnect_m0"
end="arradio.gpio_s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x9000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="c5soc.sys_cpu_interconnect_m0"
end="arradio.spi_ad9361_spi_control_port">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="15.0" start="sys_clk.clk" end="c5soc.sys_clk" />
<connection kind="clock" version="15.0" start="sys_clk.clk" end="arradio.sys_clk" />
<connection kind="clock" version="15.1" start="sys_clk.clk" end="c5soc.sys_clk" />
<connection kind="clock" version="15.1" start="sys_clk.clk" end="arradio.sys_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="c5soc.mem_clk"
end="arradio.mem_clk" />
<connection
kind="interrupt"
version="15.0"
version="15.1"
start="c5soc.sys_intr"
end="arradio.axi_dmac_adc_intr">
<parameter name="irqNumber" value="2" />
</connection>
<connection
kind="interrupt"
version="15.0"
version="15.1"
start="c5soc.sys_intr"
end="arradio.axi_dmac_dac_intr">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
version="15.0"
version="15.1"
start="c5soc.sys_intr"
end="arradio.spi_ad9361_irq">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_clk.clk_reset"
end="c5soc.sys_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_clk.clk_reset"
end="arradio.sys_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="c5soc.mem_rst"
end="arradio.mem_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

2
projects/arradio/c5soc/system_project.tcl
View File

@ -5,7 +5,7 @@ source ../../scripts/adi_env.tcl
project_new arradio_c5soc -overwrite
source "../../common/c5soc/c5soc_system_assign.tcl"
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/c5soc;../../../library/**/*"
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/**/*;../../../library/**/*"
set_global_assignment -name QSYS_FILE system_bd.qsys

120
projects/arradio/common/arradio_bd.qsys
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@ -9,14 +9,6 @@
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element ad9361_clk_bridge
{
datum _sortIndex
@ -86,6 +78,14 @@
type = "String";
}
}
element arradio_bd
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element axi_ad9361
{
datum _sortIndex
@ -330,7 +330,7 @@
<module
name="ad9361_clk_bridge"
kind="altera_clock_bridge"
version="15.0"
version="15.1"
enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
@ -359,7 +359,7 @@
<parameter name="DMA_TYPE_SRC" value="2" />
<parameter name="FIFO_SIZE" value="4" />
<parameter name="ID" value="0" />
<parameter name="SYNC_TRANSFER_START" value="0" />
<parameter name="SYNC_TRANSFER_START" value="1" />
</module>
<module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
@ -382,7 +382,7 @@
<parameter name="CHANNEL_DATA_WIDTH" value="16" />
<parameter name="NUM_OF_CHANNELS" value="4" />
</module>
<module name="gpio" kind="altera_avalon_pio" version="15.0" enabled="1">
<module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
@ -396,19 +396,19 @@
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="5" />
</module>
<module name="mem_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
<module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="mem_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
<module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
<parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" />
</module>
<module name="spi_ad9361" kind="altera_avalon_spi" version="15.0" enabled="1">
<module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
<parameter name="avalonSpec" value="2.0" />
<parameter name="clockPhase" value="0" />
<parameter name="clockPolarity" value="1" />
@ -424,84 +424,82 @@
<parameter name="targetClockRate" value="50000000" />
<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
</module>
<module name="sys_clk" kind="altera_clock_bridge" version="15.0" enabled="1">
<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
<parameter name="DERIVED_CLOCK_RATE" value="0" />
<parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
</module>
<module name="sys_rst" kind="altera_reset_bridge" version="15.0" enabled="1">
<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
<parameter name="ACTIVE_LOW_RESET" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
<parameter name="NUM_RESET_OUTPUTS" value="1" />
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
<parameter name="SYNCHRONOUS_EDGES" value="none" />
<parameter name="USE_RESET_REQUEST" value="0" />
</module>
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9361.if_l_clk"
end="adc_pack.if_adc_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9361.if_l_clk"
end="dac_upack.if_dac_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9361.if_l_clk"
end="axi_dmac_dac.if_fifo_rd_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9361.if_l_clk"
end="axi_dmac_adc.if_fifo_wr_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="axi_ad9361.if_l_clk"
end="ad9361_clk_bridge.in_clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="spi_ad9361.clk" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="sys_rst.clk" />
<connection kind="clock" version="15.0" start="mem_clk.out_clk" end="mem_rst.clk" />
<connection kind="clock" version="15.0" start="sys_clk.out_clk" end="gpio.clk" />
<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9361.delay_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="axi_dmac_adc.m_dest_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="mem_clk.out_clk"
end="axi_dmac_dac.m_src_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_ad9361.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_dmac_adc.s_axi_clock" />
<connection
kind="clock"
version="15.0"
version="15.1"
start="sys_clk.out_clk"
end="axi_dmac_dac.s_axi_clock" />
<connection
kind="conduit"
version="15.0"
version="15.1"
start="dac_upack.fifo_ch_0"
end="axi_ad9361.fifo_ch_0_out">
<parameter name="endPort" value="" />
@ -512,7 +510,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9361.fifo_ch_0_in"
end="adc_pack.fifo_ch_0">
<parameter name="endPort" value="" />
@ -523,7 +521,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9361.fifo_ch_1_in"
end="adc_pack.fifo_ch_1">
<parameter name="endPort" value="" />
@ -534,7 +532,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9361.fifo_ch_1_out"
end="dac_upack.fifo_ch_1">
<parameter name="endPort" value="" />
@ -545,7 +543,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9361.fifo_ch_2_in"
end="adc_pack.fifo_ch_2">
<parameter name="endPort" value="" />
@ -556,7 +554,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9361.fifo_ch_2_out"
end="dac_upack.fifo_ch_2">
<parameter name="endPort" value="" />
@ -567,7 +565,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9361.fifo_ch_3_in"
end="adc_pack.fifo_ch_3">
<parameter name="endPort" value="" />
@ -578,7 +576,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_ad9361.fifo_ch_3_out"
end="dac_upack.fifo_ch_3">
<parameter name="endPort" value="" />
@ -589,7 +587,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="adc_pack.if_adc_data"
end="axi_dmac_adc.if_fifo_wr_din">
<parameter name="endPort" value="" />
@ -600,7 +598,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="adc_pack.if_adc_sync"
end="axi_dmac_adc.if_fifo_wr_sync">
<parameter name="endPort" value="" />
@ -611,7 +609,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="adc_pack.if_adc_valid"
end="axi_dmac_adc.if_fifo_wr_en">
<parameter name="endPort" value="" />
@ -622,7 +620,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="dac_upack.if_dac_data"
end="axi_dmac_dac.if_fifo_rd_dout">
<parameter name="endPort" value="" />
@ -633,7 +631,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="dac_upack.if_dma_xfer_in"
end="axi_dmac_dac.if_fifo_rd_xfer_req">
<parameter name="endPort" value="" />
@ -644,7 +642,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_dmac_dac.if_fifo_rd_en"
end="dac_upack.if_dac_valid">
<parameter name="endPort" value="" />
@ -655,7 +653,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_dmac_dac.if_fifo_rd_underflow"
end="axi_ad9361.if_dac_dunf">
<parameter name="endPort" value="" />
@ -666,7 +664,7 @@
</connection>
<connection
kind="conduit"
version="15.0"
version="15.1"
start="axi_dmac_adc.if_fifo_wr_overflow"
end="axi_ad9361.if_adc_dovf">
<parameter name="endPort" value="" />
@ -677,52 +675,52 @@
</connection>
<connection
kind="reset"
version="15.0"
version="15.1"
start="axi_ad9361.if_rst"
end="adc_pack.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="adc_pack.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="adc_pack.if_adc_rst" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="axi_dmac_adc.m_dest_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="mem_rst.out_reset"
end="axi_dmac_dac.m_src_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="spi_ad9361.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="gpio.reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_ad9361.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_dmac_adc.s_axi_reset" />
<connection
kind="reset"
version="15.0"
version="15.1"
start="sys_rst.out_reset"
end="axi_dmac_dac.s_axi_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />

197
projects/common/c5soc/c5soc_system_bd.qsys
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