From 43e9b0c7a6fdb87599cd235fc926ebf5e7222c13 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 19:08:33 +0200 Subject: [PATCH] common: Disable TTC0 MMIO routing for PS7 We do not use the ttc0 to MMIO routing, but it is enabled by default, so explicitly disable it. --- projects/common/mitx045/mitx045_system_bd.tcl | 1 + projects/common/zc702/zc702_system_bd.tcl | 1 + projects/common/zc706/zc706_system_bd.tcl | 1 + projects/common/zed/zed_system_bd.tcl | 1 + 4 files changed, 4 insertions(+) diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index fc4644d97..a2a17dc0d 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -33,6 +33,7 @@ set i2s_sdata_in [create_bd_port -dir I i2s_sdata_in] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7] set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET "$ad_hdl_dir/projects/common/mitx045/mitx045.xml" ] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} ] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 4da63ea38..9ff2f95c8 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -26,6 +26,7 @@ set spdif [create_bd_port -dir O spdif] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7] set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC702}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index f1aff8288..697c6ad72 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -26,6 +26,7 @@ set spdif [create_bd_port -dir O spdif] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7] set_property -dict [list CONFIG.preset {ZC706}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index cdc48e275..44ae49eb6 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -45,6 +45,7 @@ set spdif [create_bd_port -dir O spdif] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7] set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7