From 43f460e7444a676dff7fa1d43473c775f4d3496f Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 12 Feb 2018 14:14:30 +0200 Subject: [PATCH] ad_dds_cordic_pipe.v: Optimize for implementation The present changes make better use of the Carry Chain blocks resulting in fewer FPGA resources being used. --- library/common/ad_dds_cordic_pipe.v | 41 ++++++++++++----------------- 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/library/common/ad_dds_cordic_pipe.v b/library/common/ad_dds_cordic_pipe.v index 548c9439d..3a12f5b53 100644 --- a/library/common/ad_dds_cordic_pipe.v +++ b/library/common/ad_dds_cordic_pipe.v @@ -45,17 +45,17 @@ module ad_dds_cordic_pipe#( // interface - input clk, - (* keep = "TRUE" *) input dir, - (* keep = "TRUE" *) input signed [ DW-1:0] dataa_x, - (* keep = "TRUE" *) input signed [ DW-1:0] dataa_y, - (* keep = "TRUE" *) input signed [ DW-1:0] dataa_z, - (* keep = "TRUE" *) input signed [ DW-1:0] datab_x, - (* keep = "TRUE" *) input signed [ DW-1:0] datab_y, - (* keep = "TRUE" *) input signed [ DW-1:0] datab_z, - (* keep = "TRUE" *) output reg signed [ DW-1:0] result_x, - (* keep = "TRUE" *) output reg signed [ DW-1:0] result_y, - (* keep = "TRUE" *) output reg signed [ DW-1:0] result_z, + input clk, + (* keep = "TRUE" *) input dir, + (* keep = "TRUE" *) input [ DW-1:0] dataa_x, + (* keep = "TRUE" *) input [ DW-1:0] dataa_y, + (* keep = "TRUE" *) input [ DW-1:0] dataa_z, + (* keep = "TRUE" *) input [ DW-1:0] datab_x, + (* keep = "TRUE" *) input [ DW-1:0] datab_y, + (* keep = "TRUE" *) input [ DW-1:0] datab_z, + (* keep = "TRUE" *) output reg [ DW-1:0] result_x, + (* keep = "TRUE" *) output reg [ DW-1:0] result_y, + (* keep = "TRUE" *) output reg [ DW-1:0] result_z, output signed [ DW-1:0] sgn_shift_x, output signed [ DW-1:0] sgn_shift_y, input [DELAY_DW:1] data_delay_in, @@ -66,22 +66,15 @@ module ad_dds_cordic_pipe#( reg [DELAY_DW:1] data_delay = 'd0; + wire dir_inv = ~dir; + // stage rotation always @(posedge clk) begin - case(dir) - 1'b0: begin - result_x <= dataa_x - datab_y; - result_y <= dataa_y + datab_x; - result_z <= dataa_z - datab_z; - end - 1'b1: begin - result_x <= dataa_x + datab_y; - result_y <= dataa_y - datab_x; - result_z <= dataa_z + datab_z; - end - endcase + result_x <= dataa_x + ({DW{dir_inv}} ^ datab_y) + dir_inv; + result_y <= dataa_y + ({DW{dir}} ^ datab_x) + dir; + result_z <= dataa_z + ({DW{dir_inv}} ^ datab_z) + dir_inv; end // stage shift @@ -100,4 +93,4 @@ module ad_dds_cordic_pipe#( assign data_delay_out = data_delay; -endmodule \ No newline at end of file +endmodule