From 4b19646ed92cc1f1ef8cfe8578802bc2c04a8892 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 21 Oct 2014 16:34:28 +0300 Subject: [PATCH 1/9] ad9434_fmc: Fix samples order. Four consecutive samples were reversed. --- library/axi_ad9434/axi_ad9434_if.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v index f7a723d35..2f77282bb 100644 --- a/library/axi_ad9434/axi_ad9434_if.v +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -219,10 +219,10 @@ module axi_ad9434_if ( .rst(adc_rst), .clk(adc_clk_in), .div_clk(adc_div_clk), - .data_s0(adc_data[(0*12)+l_inst]), - .data_s1(adc_data[(1*12)+l_inst]), - .data_s2(adc_data[(2*12)+l_inst]), - .data_s3(adc_data[(3*12)+l_inst]), + .data_s0(adc_data[(3*12)+l_inst]), + .data_s1(adc_data[(2*12)+l_inst]), + .data_s2(adc_data[(1*12)+l_inst]), + .data_s3(adc_data[(0*12)+l_inst]), .data_s4(), .data_s5(), .data_s6(), From 767179dce9ce9e99568ee3cd6b913bc0c8dc2d33 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 21 Oct 2014 17:44:28 +0300 Subject: [PATCH 2/9] adv7511_zc706: Fix IRQ layout Fix IRQ connection, this layout works on Linux --- projects/adv7511/zc706/system_bd.tcl | 1 - projects/common/zc706/zc706_system_bd.tcl | 7 ++++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/projects/adv7511/zc706/system_bd.tcl b/projects/adv7511/zc706/system_bd.tcl index 237319a86..e16e59ee1 100644 --- a/projects/adv7511/zc706/system_bd.tcl +++ b/projects/adv7511/zc706/system_bd.tcl @@ -2,7 +2,6 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7 set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set_property LEFT 31 [get_bd_ports GPIO_I] set_property LEFT 31 [get_bd_ports GPIO_O] diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 2c1cdad70..c2c17a12e 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -37,12 +37,13 @@ set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect @@ -114,7 +115,7 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sy connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] -connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt] +connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt] connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P] @@ -168,7 +169,7 @@ connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_ connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync] connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret] -connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut] +connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut] # spdif audio From 1d26639d7364223e5ef04b49ab34057e4be660df Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 22 Oct 2014 10:05:55 +0300 Subject: [PATCH 3/9] common: Added synchronization mechanism to the up_adc_common module --- library/common/up_adc_common.v | 52 ++++++++++++++++++++++++++++------ 1 file changed, 44 insertions(+), 8 deletions(-) diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index 3562d114e..5b7a6ece0 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -53,9 +53,12 @@ module up_adc_common ( adc_ddr_edgesel, adc_pin_mode, adc_status, + adc_sync_status, adc_status_ovf, adc_status_unf, adc_clk_ratio, + adc_start_code, + adc_sync, // channel interface @@ -124,9 +127,12 @@ module up_adc_common ( output adc_ddr_edgesel; output adc_pin_mode; input adc_status; + input adc_sync_status; input adc_status_ovf; input adc_status_unf; input [31:0] adc_clk_ratio; + output [31:0] adc_start_code; + output adc_sync; // channel interface @@ -199,6 +205,8 @@ module up_adc_common ( reg up_status_unf = 'd0; reg [ 7:0] up_usr_chanmax = 'd0; reg [31:0] up_adc_gpio_out = 'd0; + reg [31:0] up_adc_start_code = 'd0; + reg up_adc_sync = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; @@ -209,8 +217,10 @@ module up_adc_common ( wire up_preset_s; wire up_mmcm_preset_s; wire up_status_s; + wire up_sync_status_s; wire up_status_ovf_s; wire up_status_unf_s; + wire up_cntrl_xfer_done; wire [31:0] up_adc_clk_count_s; wire [ 4:0] up_delay_rdata_s; wire up_delay_status_s; @@ -249,6 +259,7 @@ module up_adc_common ( up_status_unf <= 'd0; up_usr_chanmax <= 'd0; up_adc_gpio_out <= 'd0; + up_adc_start_code <= 'd0; end else begin up_wack <= up_wreq_s; if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin @@ -258,6 +269,13 @@ module up_adc_common ( up_mmcm_resetn <= up_wdata[1]; up_resetn <= up_wdata[0]; end + if (up_adc_sync == 1'b1) begin + if (up_cntrl_xfer_done == 1'b1) begin + up_adc_sync <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin + up_adc_sync <= up_wdata[3]; + end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin up_adc_r1_mode <= up_wdata[2]; up_adc_ddr_edgesel <= up_wdata[1]; @@ -288,6 +306,9 @@ module up_adc_common ( if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin up_usr_chanmax <= up_wdata[7:0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin + up_adc_start_code <= up_wdata[31:0]; + end if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin up_adc_gpio_out <= up_wdata; end @@ -308,17 +329,19 @@ module up_adc_common ( 8'h01: up_rdata <= PCORE_ID; 8'h02: up_rdata <= up_scratch; 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; - 8'h11: up_rdata <= {29'd0, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; + 8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; 8'h15: up_rdata <= up_adc_clk_count_s; 8'h16: up_rdata <= adc_clk_ratio; 8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; 8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata}; 8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s}; + 8'h1a: up_rdata <= {31'd0, up_sync_status_s}; 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; 8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s}; 8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0}; 8'h23: up_rdata <= 32'd8; 8'h28: up_rdata <= {24'd0, adc_usr_chanmax}; + 8'h29: up_rdata <= up_adc_start_code; 8'h2e: up_rdata <= up_adc_gpio_in; 8'h2f: up_rdata <= up_adc_gpio_out; default: up_rdata <= 0; @@ -338,31 +361,44 @@ module up_adc_common ( // adc control & status - up_xfer_cntrl #(.DATA_WIDTH(3)) i_adc_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(4)) i_adc_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), - .up_data_cntrl ({ up_adc_r1_mode, + .up_data_cntrl ({ up_adc_sync, + up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}), - .up_xfer_done (), + .up_xfer_done (up_cntrl_xfer_done), .d_rst (adc_rst), .d_clk (adc_clk), - .d_data_cntrl ({ adc_r1_mode, + .d_data_cntrl ({ adc_sync, + adc_r1_mode, adc_ddr_edgesel, adc_pin_mode})); - up_xfer_status #(.DATA_WIDTH(3)) i_adc_xfer_status ( + up_xfer_status #(.DATA_WIDTH(4)) i_adc_xfer_status ( .up_rstn (up_rstn), .up_clk (up_clk), - .up_data_status ({up_status_s, + .up_data_status ({up_sync_status_s, + up_status_s, up_status_ovf_s, up_status_unf_s}), .d_rst (adc_rst), .d_clk (adc_clk), - .d_data_status ({ adc_status, + .d_data_status ({ adc_sync_status, + adc_status, adc_status_ovf, adc_status_unf})); + up_xfer_cntrl #(.DATA_WIDTH(32)) i_adc_xfer_start_code ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl (up_adc_start_code), + .up_xfer_done (), + .d_rst (adc_rst), + .d_clk (adc_clk), + .d_data_cntrl (adc_start_code)); + // adc clock monitor up_clock_mon i_adc_clock_mon ( From 17675863e00363da3f4b49640b3f97d58683c353 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 22 Oct 2014 11:48:08 +0300 Subject: [PATCH 4/9] all_projects: Fix the interrupt connections to preserve IRQ layout --- projects/ad9467_fmc/common/ad9467_bd.tcl | 2 +- projects/ad9625_fmc/common/ad9625_fmc_bd.tcl | 6 +++--- projects/ad9625x2_fmc/common/ad9625x2_fmc_bd.tcl | 7 +++---- projects/ad9671_fmc/common/ad9671_fmc_bd.tcl | 2 +- projects/ad9680_eval/common/ad9680_eval_bd.tcl | 2 +- projects/daq1/common/daq1_bd.tcl | 4 ++-- projects/daq2/common/daq2_bd.tcl | 4 ++-- projects/daq3/common/daq3_bd.tcl | 4 ++-- projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 4 ++-- projects/fmcomms1/common/fmcomms1_bd.tcl | 4 ++-- projects/fmcomms2/common/fmcomms2_bd.tcl | 4 ++-- projects/fmcomms5/common/fmcomms5_bd.tcl | 7 +++---- projects/fmcomms6/common/fmcomms6_bd.tcl | 2 +- projects/usdrx1/common/usdrx1_bd.tcl | 4 ++-- 14 files changed, 27 insertions(+), 29 deletions(-) diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index c5d3db98b..a19d9a164 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -139,7 +139,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_data] [get_bd_pins axi_ad9467_dma/fifo_wr_din] connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_dovf] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2] + connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl b/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl index 397f75033..61797156c 100644 --- a/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl +++ b/projects/ad9625_fmc/common/ad9625_fmc_bd.tcl @@ -156,8 +156,8 @@ if {$sys_zynq == 1 } { connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o] connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t] - connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] - connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] + connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In9] } if {$sys_zynq == 1 } { @@ -210,7 +210,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_fifo connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo/dma_wvalid] [get_bd_pins axi_ad9625_dma/s_axis_valid] connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready] connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data] -connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/ad9625x2_fmc/common/ad9625x2_fmc_bd.tcl b/projects/ad9625x2_fmc/common/ad9625x2_fmc_bd.tcl index 85faa0199..c7b4b89a7 100644 --- a/projects/ad9625x2_fmc/common/ad9625x2_fmc_bd.tcl +++ b/projects/ad9625x2_fmc/common/ad9625x2_fmc_bd.tcl @@ -101,7 +101,6 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect -set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc delete_bd_objs [get_bd_nets sys_concat_intc_din_2] delete_bd_objs [get_bd_ports unc_int2] @@ -120,8 +119,8 @@ connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o] connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t] -connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] -connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] +connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] +connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In9] # connections (gt) @@ -193,7 +192,7 @@ connect_bd_net -net axi_ad9625_dma_adc_dsync [get_bd_pins axi_ad9625_dm connect_bd_net -net axi_ad9625_dma_adc_ddata [get_bd_pins axi_ad9625_dma/fifo_wr_din] [get_bd_ports dma_data] connect_bd_net -net axi_ad9625_dma_adc_dovf [get_bd_pins axi_ad9625_0_core/adc_dovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl index 595e3d9b3..3363e46c9 100755 --- a/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl +++ b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl @@ -135,7 +135,7 @@ connect_bd_net -net axi_ad9671_core_adc_dwr [get_bd_ports dma_wr] connect_bd_net -net axi_ad9671_core_adc_dsync [get_bd_ports dma_sync] [get_bd_pins axi_ad9671_dma/fifo_wr_sync] connect_bd_net -net axi_ad9671_core_adc_ddata [get_bd_ports dma_data] [get_bd_pins axi_ad9671_dma/fifo_wr_din] connect_bd_net -net axi_ad9671_core_adc_dovf [get_bd_pins axi_ad9671_core/adc_dovf] [get_bd_pins axi_ad9671_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/ad9680_eval/common/ad9680_eval_bd.tcl b/projects/ad9680_eval/common/ad9680_eval_bd.tcl index eb8166e1d..e615df9d0 100644 --- a/projects/ad9680_eval/common/ad9680_eval_bd.tcl +++ b/projects/ad9680_eval/common/ad9680_eval_bd.tcl @@ -97,7 +97,7 @@ connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index af271b0de..f95e5a068 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -175,7 +175,7 @@ connect_bd_net -net axi_ad9250_adc_dovf [get_bd_pins axi_ad9250_core/a connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports adc_dwr] connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports adc_dsync] connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports adc_ddata] -connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In13] connect_bd_net -net axi_ad9250_adc_clk [get_bd_ports adc_clk] @@ -199,7 +199,7 @@ connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122_core/d connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_drd] connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_ddata] connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow] -connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12] connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_ports dac_clk] diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 93eb6fad2..0ce74ff49 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -272,7 +272,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] + connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In12] # connections (adc) @@ -304,7 +304,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] # dac/adc clocks diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index b16cb692a..b46a8cb2a 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -299,7 +299,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9152_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9152_dma/fifo_rd_en] connect_bd_net -net axi_ad9152_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9152_dma/fifo_rd_dout] connect_bd_net -net axi_ad9152_dac_dunf [get_bd_pins axi_ad9152_core/dac_dunf] [get_bd_pins axi_ad9152_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In3] + connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In12] # connections (adc) @@ -341,7 +341,7 @@ if {$sys_zynq == 1} { connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid] connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready] connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data] - connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] } # dac/adc clocks diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index 2ee0041a8..aafa0b879 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -216,8 +216,8 @@ connect_bd_net -net axi_ad9250_1_dma_data [get_bd_pins axi_ad9250_1_dm connect_bd_net -net axi_ad9250_0_adc_dovf [get_bd_pins axi_ad9250_0_core/adc_dovf] [get_bd_pins axi_ad9250_0_dma/fifo_wr_overflow] connect_bd_net -net axi_ad9250_1_adc_dovf [get_bd_pins axi_ad9250_1_core/adc_dovf] [get_bd_pins axi_ad9250_1_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In2] -connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In13] +connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In12] # interconnect (cpu) diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 38e172632..f36f9b432 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -128,7 +128,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_dma_rd] connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_dma_rdata] - connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3] + connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12] # connections (adc) @@ -160,7 +160,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9643_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9643_dma/fifo_wr_sync] connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din] connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2] + connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 70a97841d..ce30eac92 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -251,8 +251,8 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In5] connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In6] } else { - connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2] - connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12] } # interconnect (cpu) diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl index 68d39d248..2ec8e447d 100644 --- a/projects/fmcomms5/common/fmcomms5_bd.tcl +++ b/projects/fmcomms5/common/fmcomms5_bd.tcl @@ -129,8 +129,7 @@ if {$sys_zynq == 0} { set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_intc } else { set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect - set_property -dict [list CONFIG.NUM_PORTS {6}] $sys_concat_intc -} +} if {$sys_zynq == 1} { set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 @@ -277,9 +276,9 @@ connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0 connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] connect_bd_net -net axi_ad9361_fifo_valid [get_bd_pins util_dac_unpack_0/fifo_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13] connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] -connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12] # interconnect (cpu) diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl index 56a0ece8c..623ab83cd 100644 --- a/projects/fmcomms6/common/fmcomms6_bd.tcl +++ b/projects/fmcomms6/common/fmcomms6_bd.tcl @@ -165,7 +165,7 @@ connect_bd_net -net axi_ad9652_dma_dwr [get_bd_pins sys_wfifo/s_wr] connect_bd_net -net axi_ad9652_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9652_dma/fifo_wr_sync] connect_bd_net -net axi_ad9652_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9652_dma/fifo_wr_din] connect_bd_net -net axi_ad9652_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9652_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 45682451a..a11d7d1bc 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -132,7 +132,7 @@ connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_u connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] -connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12] # connections (gt) @@ -193,7 +193,7 @@ connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en] connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data] connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf] -connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In13] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_0/adc_raddr_out] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in] From 121a41691601437309253e9cf0c053e1ce4f9686 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 22 Oct 2014 13:07:55 +0300 Subject: [PATCH 5/9] axi_dmac: Fixed constraints for axi_dmac core --- library/axi_dmac/axi_dmac_constr.tcl | 24 ++++++++++++++++++++++++ library/axi_dmac/axi_dmac_constr.xdc | 4 ---- library/axi_dmac/axi_dmac_ip.tcl | 4 ++-- 3 files changed, 26 insertions(+), 6 deletions(-) create mode 100644 library/axi_dmac/axi_dmac_constr.tcl delete mode 100644 library/axi_dmac/axi_dmac_constr.xdc diff --git a/library/axi_dmac/axi_dmac_constr.tcl b/library/axi_dmac/axi_dmac_constr.tcl new file mode 100644 index 000000000..7a5a80fa0 --- /dev/null +++ b/library/axi_dmac/axi_dmac_constr.tcl @@ -0,0 +1,24 @@ + +if { [get_clocks -quiet -of_objects [get_ports s_axi_aclk]] != ""} { + set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]] +} + +if { [get_clocks -quiet -of_objects [get_ports m_dest_axi_aclk]] != ""} { + set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_dest_axi_aclk]] +} + +if { [get_clocks -quiet -of_objects [get_ports m_src_axi_aclk]] != ""} { + set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_src_axi_aclk]] +} + +if { [get_clocks -quiet -of_objects [get_ports s_axis_aclk]] != ""} { + set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axis_aclk]] +} + +if { [get_clocks -quiet -of_objects [get_ports m_axis_aclk]] != ""} { + set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_aclk]] +} + +if { [get_clocks -quiet -of_objects [get_ports fifo_rd_clk]] != ""} { + set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_rd_clk]] +} diff --git a/library/axi_dmac/axi_dmac_constr.xdc b/library/axi_dmac/axi_dmac_constr.xdc deleted file mode 100644 index fd40910d9..000000000 --- a/library/axi_dmac/axi_dmac_constr.xdc +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index cf5b6ad18..a443a1ad9 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -29,11 +29,11 @@ adi_ip_files axi_dmac [list \ "response_generator.v" \ "axi_dmac.v" \ "axi_repack.v" \ - "axi_dmac_constr.xdc" ] + "axi_dmac_constr.tcl" ] adi_ip_properties axi_dmac adi_ip_constraints axi_dmac [list \ - "axi_dmac_constr.xdc" ] + "axi_dmac_constr.tcl" ] set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \ [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]] From fe92b8b210c8b5bb737c80bc8d24e6b33c13d3b6 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 22 Oct 2014 13:10:28 +0300 Subject: [PATCH 6/9] axi_ad9671: Updated synchronization mechanism to have a software defined starting code --- library/axi_ad9671/axi_ad9671.v | 38 ++++++++++++++++++++------ library/axi_ad9671/axi_ad9671_if.v | 44 ++++++++++++++++++++---------- 2 files changed, 59 insertions(+), 23 deletions(-) diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 3e41ffc9b..a0102b213 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -41,7 +41,7 @@ module axi_ad9671 ( - // jesd interface + // jesd interface // rx_clk is (line-rate/40) rx_clk, @@ -56,6 +56,8 @@ module axi_ad9671 ( adc_data, adc_dovf, adc_dunf, + adc_sync_in, + adc_sync_out, adc_raddr_in, adc_raddr_out, @@ -89,7 +91,7 @@ module axi_ad9671 ( parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; parameter C_S_AXI_MIN_SIZE = 32'hffff; - // jesd interface + // jesd interface // rx_clk is the jesd clock (ref_clk/2) input rx_clk; @@ -104,6 +106,8 @@ module axi_ad9671 ( output [127:0] adc_data; input adc_dovf; input adc_dunf; + input adc_sync_in; + output adc_sync_out; input [ 3:0] adc_raddr_in; output [ 3:0] adc_raddr_out; @@ -149,6 +153,7 @@ module axi_ad9671 ( // internal signals wire adc_status_s; + wire adc_sync_status_s; wire adc_valid_s; wire [ 15:0] adc_data_s[7:0]; wire [ 7:0] adc_or_s; @@ -163,6 +168,8 @@ module axi_ad9671 ( wire [ 31:0] up_rdata_s[8:0]; wire up_rack_s[8:0]; wire up_wack_s[8:0]; + wire [ 31:0] adc_start_code; + wire adc_sync; // signal name changes @@ -194,7 +201,10 @@ module axi_ad9671 ( // main (device interface) - axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N), .PCORE_ID(PCORE_ID)) i_if ( + axi_ad9671_if #( + .PCORE_4L_2L_N(PCORE_4L_2L_N), + .PCORE_ID(PCORE_ID) + ) i_if ( .rx_clk (rx_clk), .rx_data (rx_data), .rx_data_sof (rx_data_sof), @@ -217,6 +227,11 @@ module axi_ad9671 ( .adc_or_g (adc_or_s[6]), .adc_data_h (adc_data_s[7]), .adc_or_h (adc_or_s[7]), + .adc_start_code (adc_start_code), + .adc_sync (adc_sync), + .adc_sync_in (adc_sync_in), + .adc_sync_out (adc_sync_out), + .adc_sync_status (adc_sync_status_s), .adc_status (adc_status_s), .adc_raddr_in(adc_raddr_in), .adc_raddr_out(adc_raddr_out)); @@ -253,13 +268,18 @@ module axi_ad9671 ( // common processor control - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + up_adc_common #( + .PCORE_ID(PCORE_ID) + ) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_r1_mode (), .adc_ddr_edgesel (), .adc_pin_mode (), + .adc_start_code (adc_start_code), + .adc_sync (adc_sync), + .adc_sync_status (adc_sync_status_s), .adc_status (adc_status_s), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index e6df14615..51061132f 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -70,6 +70,11 @@ module axi_ad9671_if ( adc_or_g, adc_data_h, adc_or_h, + adc_start_code, + adc_sync_in, + adc_sync_out, + adc_sync, + adc_sync_status, adc_status, adc_raddr_in, adc_raddr_out); @@ -107,6 +112,11 @@ module axi_ad9671_if ( output adc_or_g; output [ 15:0] adc_data_h; output adc_or_h; + input [ 31:0] adc_start_code; + input adc_sync_in; + output adc_sync_out; + input adc_sync; + output adc_sync_status; output adc_status; input [ 3:0] adc_raddr_in; output [ 3:0] adc_raddr_out; @@ -124,13 +134,14 @@ module axi_ad9671_if ( wire [ 15:0] adc_data_g_s; wire [ 15:0] adc_data_h_s; wire [ 3:0] adc_raddr_s; + wire adc_sync_s; // internal registers reg int_valid = 'd0; reg [127:0] int_data = 'd0; reg adc_status = 'd0; - reg adc_start = 'd0; + reg adc_sync_status = 'd0; reg [ 3:0] adc_waddr = 'd0; reg [ 3:0] adc_raddr_out = 'd0; @@ -146,7 +157,8 @@ module axi_ad9671_if ( // adc clock & valid assign adc_clk = rx_clk; - assign adc_valid = int_valid & adc_start; + assign adc_valid = int_valid; + assign adc_sync_out = adc_sync; assign adc_or_a = 'd0; assign adc_or_b = 'd0; @@ -170,9 +182,9 @@ module axi_ad9671_if ( adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s}; assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in; + assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in; - always @(posedge rx_clk) - begin + always @(posedge rx_clk) begin adc_data_a <= adc_rdata[ 15: 0]; adc_data_b <= adc_rdata[ 31: 16]; adc_data_c <= adc_rdata[ 47: 32]; @@ -185,17 +197,21 @@ module axi_ad9671_if ( always @(posedge rx_clk) begin if (adc_rst == 1'b1) begin - adc_waddr <= 4'h0; - adc_raddr_out <= 4'h8; - adc_start <= 1'b0; - end - else begin - if (int_valid == 1'b1 && adc_data_a_s == 16'hbeef) begin - adc_start <= 1'b1; + adc_waddr <= 4'h0; + adc_raddr_out <= 4'h8; + adc_sync_status <= 1'b0; + end else begin + if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin + adc_sync_status <= 1'b0; + end else if(adc_sync_s == 1'b1) begin + adc_sync_status <= 1'b1; end - if (int_valid == 1'b1 && adc_start == 1'b1) begin - adc_waddr <= adc_waddr + 1; - adc_raddr_out <= adc_raddr_out + 1; + if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin + adc_waddr <= 4'h0; + adc_raddr_out <= 4'h8; + end else if (int_valid == 1'b1) begin + adc_waddr <= adc_waddr + 1; + adc_raddr_out <= adc_raddr_out + 1; end end end From cd9033296cc750a84e58d5e60f4be218f3db99c1 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 22 Oct 2014 13:14:59 +0300 Subject: [PATCH 7/9] ad9671_fmc: Fixed constraint files --- projects/ad9671_fmc/zc706/system_constr.xdc | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/projects/ad9671_fmc/zc706/system_constr.xdc b/projects/ad9671_fmc/zc706/system_constr.xdc index 8e664a266..c34799a79 100644 --- a/projects/ad9671_fmc/zc706/system_constr.xdc +++ b/projects/ad9671_fmc/zc706/system_constr.xdc @@ -37,14 +37,3 @@ set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_ad95 create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_ad9671_gt_rx_clk] -create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] - -set_clock_groups -asynchronous -group {rx_div_clk} -set_clock_groups -asynchronous -group {fmc_dma_clk} - -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] From a0d27a117c82ff90895df3418780458318282480 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 22 Oct 2014 13:20:44 +0300 Subject: [PATCH 8/9] usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints --- projects/usdrx1/common/usdrx1_bd.tcl | 60 +++++++++++++------------ projects/usdrx1/zc706/system_constr.xdc | 12 ----- 2 files changed, 32 insertions(+), 40 deletions(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index a11d7d1bc..3dceef010 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -131,25 +131,25 @@ connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_u connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o] connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12] # connections (gt) -connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk] -connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] -connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] -connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] -connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref] +connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk] +connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] +connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] +connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] +connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref] # connections (adc) connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk_g] connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk] connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset] @@ -198,6 +198,10 @@ connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_3/adc_raddr_in] +connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_0/adc_sync_out] +connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_1/adc_sync_in] +connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_2/adc_sync_in] +connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_3/adc_sync_in] # interconnect (cpu) @@ -217,14 +221,14 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sy connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source @@ -233,14 +237,14 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESET connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] # interconnect (gt es) @@ -266,7 +270,7 @@ connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] -connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] +connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source @@ -275,7 +279,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk] connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source -connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] # ila diff --git a/projects/usdrx1/zc706/system_constr.xdc b/projects/usdrx1/zc706/system_constr.xdc index e8af4bfd6..4386c3814 100644 --- a/projects/usdrx1/zc706/system_constr.xdc +++ b/projects/usdrx1/zc706/system_constr.xdc @@ -83,15 +83,3 @@ set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk] -create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] -create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3] - -set_clock_groups -asynchronous -group {rx_div_clk} -set_clock_groups -asynchronous -group {fmc_dma_clk} - -set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] From dcdba475f731e744bf61357e1f91eae32a28d145 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 22 Oct 2014 15:40:51 +0300 Subject: [PATCH 9/9] vc707_common: Fix net name sys_100m_resetn --- projects/common/vc707/vc707_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index c9a5fa9a0..90b8ff068 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -455,7 +455,7 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] $sys_200m_clk_source -connect_bd_net -net sys_100m_reset [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]