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Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev

main
Michael Hennerich 2014-10-22 17:19:37 +02:00
parent 2beaeb9176 dcdba475f7
commit 43fe20d141
26 changed files with 197 additions and 126 deletions
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8
library/axi_ad9434/axi_ad9434_if.v
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@ -219,10 +219,10 @@ module axi_ad9434_if (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
.data_s0(adc_data[(0*12)+l_inst]),
.data_s1(adc_data[(1*12)+l_inst]),
.data_s2(adc_data[(2*12)+l_inst]),
.data_s3(adc_data[(3*12)+l_inst]),
.data_s0(adc_data[(3*12)+l_inst]),
.data_s1(adc_data[(2*12)+l_inst]),
.data_s2(adc_data[(1*12)+l_inst]),
.data_s3(adc_data[(0*12)+l_inst]),
.data_s4(),
.data_s5(),
.data_s6(),

24
library/axi_ad9671/axi_ad9671.v
View File

@ -56,6 +56,8 @@ module axi_ad9671 (
adc_data,
adc_dovf,
adc_dunf,
adc_sync_in,
adc_sync_out,
adc_raddr_in,
adc_raddr_out,
@ -104,6 +106,8 @@ module axi_ad9671 (
output [127:0] adc_data;
input adc_dovf;
input adc_dunf;
input adc_sync_in;
output adc_sync_out;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
@ -149,6 +153,7 @@ module axi_ad9671 (
// internal signals
wire adc_status_s;
wire adc_sync_status_s;
wire adc_valid_s;
wire [ 15:0] adc_data_s[7:0];
wire [ 7:0] adc_or_s;
@ -163,6 +168,8 @@ module axi_ad9671 (
wire [ 31:0] up_rdata_s[8:0];
wire up_rack_s[8:0];
wire up_wack_s[8:0];
wire [ 31:0] adc_start_code;
wire adc_sync;
// signal name changes
@ -194,7 +201,10 @@ module axi_ad9671 (
// main (device interface)
axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N), .PCORE_ID(PCORE_ID)) i_if (
axi_ad9671_if #(
.PCORE_4L_2L_N(PCORE_4L_2L_N),
.PCORE_ID(PCORE_ID)
) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.rx_data_sof (rx_data_sof),
@ -217,6 +227,11 @@ module axi_ad9671 (
.adc_or_g (adc_or_s[6]),
.adc_data_h (adc_data_s[7]),
.adc_or_h (adc_or_s[7]),
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.adc_sync_in (adc_sync_in),
.adc_sync_out (adc_sync_out),
.adc_sync_status (adc_sync_status_s),
.adc_status (adc_status_s),
.adc_raddr_in(adc_raddr_in),
.adc_raddr_out(adc_raddr_out));
@ -253,13 +268,18 @@ module axi_ad9671 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(
.PCORE_ID(PCORE_ID)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status_s),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),

36
library/axi_ad9671/axi_ad9671_if.v
View File

@ -70,6 +70,11 @@ module axi_ad9671_if (
adc_or_g,
adc_data_h,
adc_or_h,
adc_start_code,
adc_sync_in,
adc_sync_out,
adc_sync,
adc_sync_status,
adc_status,
adc_raddr_in,
adc_raddr_out);
@ -107,6 +112,11 @@ module axi_ad9671_if (
output adc_or_g;
output [ 15:0] adc_data_h;
output adc_or_h;
input [ 31:0] adc_start_code;
input adc_sync_in;
output adc_sync_out;
input adc_sync;
output adc_sync_status;
output adc_status;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
@ -124,13 +134,14 @@ module axi_ad9671_if (
wire [ 15:0] adc_data_g_s;
wire [ 15:0] adc_data_h_s;
wire [ 3:0] adc_raddr_s;
wire adc_sync_s;
// internal registers
reg int_valid = 'd0;
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
reg adc_start = 'd0;
reg adc_sync_status = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
@ -146,7 +157,8 @@ module axi_ad9671_if (
// adc clock & valid
assign adc_clk = rx_clk;
assign adc_valid = int_valid & adc_start;
assign adc_valid = int_valid;
assign adc_sync_out = adc_sync;
assign adc_or_a = 'd0;
assign adc_or_b = 'd0;
@ -170,9 +182,9 @@ module axi_ad9671_if (
adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in;
always @(posedge rx_clk)
begin
always @(posedge rx_clk) begin
adc_data_a <= adc_rdata[ 15: 0];
adc_data_b <= adc_rdata[ 31: 16];
adc_data_c <= adc_rdata[ 47: 32];
@ -187,13 +199,17 @@ module axi_ad9671_if (
if (adc_rst == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
adc_start <= 1'b0;
adc_sync_status <= 1'b0;
end else begin
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_sync_status <= 1'b0;
end else if(adc_sync_s == 1'b1) begin
adc_sync_status <= 1'b1;
end
else begin
if (int_valid == 1'b1 && adc_data_a_s == 16'hbeef) begin
adc_start <= 1'b1;
end
if (int_valid == 1'b1 && adc_start == 1'b1) begin
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
end else if (int_valid == 1'b1) begin
adc_waddr <= adc_waddr + 1;
adc_raddr_out <= adc_raddr_out + 1;
end

24
library/axi_dmac/axi_dmac_constr.tcl Normal file
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@ -0,0 +1,24 @@
if { [get_clocks -quiet -of_objects [get_ports s_axi_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports m_dest_axi_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_dest_axi_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports m_src_axi_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_src_axi_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports s_axis_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axis_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports m_axis_aclk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports m_axis_aclk]]
}
if { [get_clocks -quiet -of_objects [get_ports fifo_rd_clk]] != ""} {
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports fifo_rd_clk]]
}

4
library/axi_dmac/axi_dmac_constr.xdc
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@ -1,4 +0,0 @@

4
library/axi_dmac/axi_dmac_ip.tcl
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@ -29,11 +29,11 @@ adi_ip_files axi_dmac [list \
"response_generator.v" \
"axi_dmac.v" \
"axi_repack.v" \
"axi_dmac_constr.xdc" ]
"axi_dmac_constr.tcl" ]
adi_ip_properties axi_dmac
adi_ip_constraints axi_dmac [list \
"axi_dmac_constr.xdc" ]
"axi_dmac_constr.tcl" ]
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]

52
library/common/up_adc_common.v
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@ -53,9 +53,12 @@ module up_adc_common (
adc_ddr_edgesel,
adc_pin_mode,
adc_status,
adc_sync_status,
adc_status_ovf,
adc_status_unf,
adc_clk_ratio,
adc_start_code,
adc_sync,
// channel interface
@ -124,9 +127,12 @@ module up_adc_common (
output adc_ddr_edgesel;
output adc_pin_mode;
input adc_status;
input adc_sync_status;
input adc_status_ovf;
input adc_status_unf;
input [31:0] adc_clk_ratio;
output [31:0] adc_start_code;
output adc_sync;
// channel interface
@ -199,6 +205,8 @@ module up_adc_common (
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax = 'd0;
reg [31:0] up_adc_gpio_out = 'd0;
reg [31:0] up_adc_start_code = 'd0;
reg up_adc_sync = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -209,8 +217,10 @@ module up_adc_common (
wire up_preset_s;
wire up_mmcm_preset_s;
wire up_status_s;
wire up_sync_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire up_cntrl_xfer_done;
wire [31:0] up_adc_clk_count_s;
wire [ 4:0] up_delay_rdata_s;
wire up_delay_status_s;
@ -249,6 +259,7 @@ module up_adc_common (
up_status_unf <= 'd0;
up_usr_chanmax <= 'd0;
up_adc_gpio_out <= 'd0;
up_adc_start_code <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
@ -258,6 +269,13 @@ module up_adc_common (
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if (up_adc_sync == 1'b1) begin
if (up_cntrl_xfer_done == 1'b1) begin
up_adc_sync <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sync <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_r1_mode <= up_wdata[2];
up_adc_ddr_edgesel <= up_wdata[1];
@ -288,6 +306,9 @@ module up_adc_common (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_adc_start_code <= up_wdata[31:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_adc_gpio_out <= up_wdata;
end
@ -308,17 +329,19 @@ module up_adc_common (
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {29'd0, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
8'h15: up_rdata <= up_adc_clk_count_s;
8'h16: up_rdata <= adc_clk_ratio;
8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata};
8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s};
8'h1a: up_rdata <= {31'd0, up_sync_status_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s};
8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h23: up_rdata <= 32'd8;
8'h28: up_rdata <= {24'd0, adc_usr_chanmax};
8'h29: up_rdata <= up_adc_start_code;
8'h2e: up_rdata <= up_adc_gpio_in;
8'h2f: up_rdata <= up_adc_gpio_out;
default: up_rdata <= 0;
@ -338,31 +361,44 @@ module up_adc_common (
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(3)) i_adc_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(4)) i_adc_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_r1_mode,
.up_data_cntrl ({ up_adc_sync,
up_adc_r1_mode,
up_adc_ddr_edgesel,
up_adc_pin_mode}),
.up_xfer_done (),
.up_xfer_done (up_cntrl_xfer_done),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_r1_mode,
.d_data_cntrl ({ adc_sync,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(3)) i_adc_xfer_status (
up_xfer_status #(.DATA_WIDTH(4)) i_adc_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_status_s,
.up_data_status ({up_sync_status_s,
up_status_s,
up_status_ovf_s,
up_status_unf_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_status,
.d_data_status ({ adc_sync_status,
adc_status,
adc_status_ovf,
adc_status_unf}));
up_xfer_cntrl #(.DATA_WIDTH(32)) i_adc_xfer_start_code (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl (up_adc_start_code),
.up_xfer_done (),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl (adc_start_code));
// adc clock monitor
up_clock_mon i_adc_clock_mon (

2
projects/ad9467_fmc/common/ad9467_bd.tcl
View File

@ -139,7 +139,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_data] [get_bd_pins axi_ad9467_dma/fifo_wr_din]
connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_dovf] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)

6
projects/ad9625_fmc/common/ad9625_fmc_bd.tcl
View File

@ -156,8 +156,8 @@ if {$sys_zynq == 1 } {
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10]
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In9]
}
if {$sys_zynq == 1 } {
@ -210,7 +210,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_fifo
connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo/dma_wvalid] [get_bd_pins axi_ad9625_dma/s_axis_valid]
connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)

7
projects/ad9625x2_fmc/common/ad9625x2_fmc_bd.tcl
View File

@ -101,7 +101,6 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
delete_bd_objs [get_bd_ports unc_int2]
@ -120,8 +119,8 @@ connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10]
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In9]
# connections (gt)
@ -193,7 +192,7 @@ connect_bd_net -net axi_ad9625_dma_adc_dsync [get_bd_pins axi_ad9625_dm
connect_bd_net -net axi_ad9625_dma_adc_ddata [get_bd_pins axi_ad9625_dma/fifo_wr_din] [get_bd_ports dma_data]
connect_bd_net -net axi_ad9625_dma_adc_dovf [get_bd_pins axi_ad9625_0_core/adc_dovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)

2
projects/ad9671_fmc/common/ad9671_fmc_bd.tcl
View File

@ -135,7 +135,7 @@ connect_bd_net -net axi_ad9671_core_adc_dwr [get_bd_ports dma_wr]
connect_bd_net -net axi_ad9671_core_adc_dsync [get_bd_ports dma_sync] [get_bd_pins axi_ad9671_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9671_core_adc_ddata [get_bd_ports dma_data] [get_bd_pins axi_ad9671_dma/fifo_wr_din]
connect_bd_net -net axi_ad9671_core_adc_dovf [get_bd_pins axi_ad9671_core/adc_dovf] [get_bd_pins axi_ad9671_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)

11
projects/ad9671_fmc/zc706/system_constr.xdc
View File

@ -37,14 +37,3 @@ set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_ad95
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_ad9671_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9671_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

2
projects/ad9680_eval/common/ad9680_eval_bd.tcl
View File

@ -97,7 +97,7 @@ connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core
connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din]
connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)

1
projects/adv7511/zc706/system_bd.tcl
View File

@ -2,7 +2,6 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
set_property LEFT 31 [get_bd_ports GPIO_I]
set_property LEFT 31 [get_bd_ports GPIO_O]

2
projects/common/vc707/vc707_system_bd.tcl
View File

@ -455,7 +455,7 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S
connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] $sys_200m_clk_source
connect_bd_net -net sys_100m_reset [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]

7
projects/common/zc706/zc706_system_bd.tcl
View File

@ -37,12 +37,13 @@ set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
@ -114,7 +115,7 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sy
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt]
connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
@ -168,7 +169,7 @@ connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut]
connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut]
# spdif audio

4
projects/daq1/common/daq1_bd.tcl
View File

@ -175,7 +175,7 @@ connect_bd_net -net axi_ad9250_adc_dovf [get_bd_pins axi_ad9250_core/a
connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports adc_dwr]
connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports adc_dsync]
connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports adc_ddata]
connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In13]
connect_bd_net -net axi_ad9250_adc_clk [get_bd_ports adc_clk]
@ -199,7 +199,7 @@ connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122_core/d
connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_drd]
connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_ddata]
connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12]
connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_ports dac_clk]

4
projects/daq2/common/daq2_bd.tcl
View File

@ -272,7 +272,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en]
connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In12]
# connections (adc)
@ -304,7 +304,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din]
connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
# dac/adc clocks

4
projects/daq3/common/daq3_bd.tcl
View File

@ -299,7 +299,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9152_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9152_dma/fifo_rd_en]
connect_bd_net -net axi_ad9152_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9152_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9152_dac_dunf [get_bd_pins axi_ad9152_core/dac_dunf] [get_bd_pins axi_ad9152_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In12]
# connections (adc)
@ -341,7 +341,7 @@ if {$sys_zynq == 1} {
connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
}
# dac/adc clocks

4
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
View File

@ -216,8 +216,8 @@ connect_bd_net -net axi_ad9250_1_dma_data [get_bd_pins axi_ad9250_1_dm
connect_bd_net -net axi_ad9250_0_adc_dovf [get_bd_pins axi_ad9250_0_core/adc_dovf] [get_bd_pins axi_ad9250_0_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9250_1_adc_dovf [get_bd_pins axi_ad9250_1_core/adc_dovf] [get_bd_pins axi_ad9250_1_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In13]
connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In12]
# interconnect (cpu)

4
projects/fmcomms1/common/fmcomms1_bd.tcl
View File

@ -128,7 +128,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_dma_rd]
connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_dma_rdata]
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12]
# connections (adc)
@ -160,7 +160,7 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9643_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9643_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din]
connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)

4
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -251,8 +251,8 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In6]
} else {
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12]
}
# interconnect (cpu)

5
projects/fmcomms5/common/fmcomms5_bd.tcl
View File

@ -129,7 +129,6 @@ if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_intc
} else {
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_PORTS {6}] $sys_concat_intc
}
if {$sys_zynq == 1} {
@ -277,9 +276,9 @@ connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9361_fifo_valid [get_bd_pins util_dac_unpack_0/fifo_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13]
connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12]
# interconnect (cpu)

2
projects/fmcomms6/common/fmcomms6_bd.tcl
View File

@ -165,7 +165,7 @@ connect_bd_net -net axi_ad9652_dma_dwr [get_bd_pins sys_wfifo/s_wr]
connect_bd_net -net axi_ad9652_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9652_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9652_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9652_dma/fifo_wr_din]
connect_bd_net -net axi_ad9652_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9652_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)

8
projects/usdrx1/common/usdrx1_bd.tcl
View File

@ -132,7 +132,7 @@ connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_u
connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3]
connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12]
# connections (gt)
@ -193,11 +193,15 @@ connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core
connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en]
connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data]
connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In13]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_0/adc_raddr_out]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_3/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_0/adc_sync_out]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_1/adc_sync_in]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_2/adc_sync_in]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_3/adc_sync_in]
# interconnect (cpu)

12
projects/usdrx1/zc706/system_constr.xdc
View File

@ -83,15 +83,3 @@ set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]