pzsdr1-added
Rejeesh Kutty
parent
aa77af6bdf
commit
44a382fc69
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# create board design
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# default ports
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir O spi1_csn_2_o
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create_bd_port -dir O spi1_csn_1_o
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create_bd_port -dir O spi1_csn_0_o
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create_bd_port -dir I spi1_csn_i
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create_bd_port -dir I spi1_clk_i
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create_bd_port -dir O spi1_clk_o
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create_bd_port -dir I spi1_sdo_i
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create_bd_port -dir O spi1_sdo_o
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create_bd_port -dir I spi1_sdi_i
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create_bd_port -dir I -from 63 -to 0 gpio_i
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create_bd_port -dir O -from 63 -to 0 gpio_o
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create_bd_port -dir O -from 63 -to 0 gpio_t
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# otg
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set otg_vbusoc [create_bd_port -dir I otg_vbusoc]
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_11
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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create_bd_port -dir I -type intr ps_intr_15
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# instance: sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
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source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_ps7.tcl
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
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set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
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set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
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set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
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set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
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ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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# interface connections
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ad_connect ddr sys_ps7/DDR
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ad_connect gpio_i sys_ps7/GPIO_I
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ad_connect gpio_o sys_ps7/GPIO_O
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ad_connect gpio_t sys_ps7/GPIO_T
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ad_connect fixed_io sys_ps7/FIXED_IO
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ad_connect iic_main axi_iic_main/iic
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ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
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ad_connect sys_logic_inv/Op1 otg_vbusoc
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# spi connections
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ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
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ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
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ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
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ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
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ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
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ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
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ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
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ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
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ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
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ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
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ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
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ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
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ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
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ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
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ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
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ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
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ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
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ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
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# interrupts
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ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
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ad_connect sys_concat_intc/In15 ps_intr_15
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ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In13 ps_intr_13
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ad_connect sys_concat_intc/In12 ps_intr_12
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ad_connect sys_concat_intc/In11 ps_intr_11
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ad_connect sys_concat_intc/In10 ps_intr_10
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ad_connect sys_concat_intc/In9 ps_intr_09
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ad_connect sys_concat_intc/In8 ps_intr_08
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ad_connect sys_concat_intc/In7 ps_intr_07
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ad_connect sys_concat_intc/In6 ps_intr_06
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ad_connect sys_concat_intc/In5 ps_intr_05
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ad_connect sys_concat_intc/In4 ps_intr_04
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ad_connect sys_concat_intc/In3 ps_intr_03
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ad_connect sys_concat_intc/In2 ps_intr_02
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ad_connect sys_concat_intc/In1 ps_intr_01
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ad_connect sys_concat_intc/In0 ps_intr_00
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# interconnects
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ad_cpu_interconnect 0x41600000 axi_iic_main
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# module ad9361
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source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
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source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
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set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
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@ -0,0 +1,88 @@
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# constraints
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# ad9361
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35
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set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35
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set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35
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set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35
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set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35
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set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35
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set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35
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set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35
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set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35
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set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35
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set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35
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set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35
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set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35
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set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35
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set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35
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set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35
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set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35
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set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35
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set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35
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set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35
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set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35
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set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35
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set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35
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set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35
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set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34
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set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34
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set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34
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set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34
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set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35
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set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35
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set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L23N_T3_35
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set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35
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set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports clk_out] ; ## IO_25_VRP_35
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# iic
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set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] ; ## IO_L5P_T0_13
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set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] ; ## IO_L5N_T0_13
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# gpio
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set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## (pb) IO_L12N_T1_MRCC_33
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set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## (pb) IO_L8N_T1_34
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set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## (pb) IO_L9P_T1_DQS_34
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set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## (pb) IO_L9N_T1_DQS_34
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set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## (led) IO_L17N_T2_34
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set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## (led) IO_0_12
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set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## (led) IO_25_12
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set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## (led) IO_L23P_T3_12
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set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## (dip) IO_L23N_T3_12
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set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## (dip) IO_L24P_T3_12
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set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## (dip) IO_L24N_T3_12
|
||||
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## (dip) IO_0_13
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
|
||||
create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
|
||||
set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_PACKAGE_NAME {fbg676} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET_RESET_SELECT {Separate reset pins} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_RESET_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_RESET_IO {MIO 8} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET1_RESET_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET1_RESET_IO {MIO 51} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_SD0_GRP_CD_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_SD0_GRP_CD_IO {MIO 50} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_USB0_RESET_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_USB0_RESET_IO {MIO 7} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
|
||||
## DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
|
||||
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.053} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.059} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.065} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.066} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.264} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.265} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.330} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.330} [get_bd_cells sys_ps7]
|
||||
|
||||
Loading…
Reference in New Issue