adrv9371: Add decimation and interpolation filters

main
AndreiGrozav 2019-06-24 14:16:43 +01:00 committed by AndreiGrozav
parent 36a1767329
commit 44deaadb4a
7 changed files with 54 additions and 9 deletions

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@ -33,6 +33,8 @@ source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
# ad9371
create_bd_port -dir I dac_fifo_bypass
create_bd_port -dir I adc_fir_filter_active
create_bd_port -dir I dac_fir_filter_active
# dac peripherals
@ -59,6 +61,9 @@ ad_ip_instance util_upack2 util_ad9371_tx_upack [list \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
]
ad_add_interpolation_filter "tx_fir_interpolator" 8 $TX_NUM_OF_CONVERTERS 2 {122.88} {15.36} \
"$ad_hdl_dir/library/util_fir_int/coefile_int.coe"
adi_tpl_jesd204_tx_create tx_ad9371_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
@ -121,6 +126,9 @@ ad_ip_parameter axi_ad9371_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
ad_add_decimation_filter "rx_fir_decimator" 8 $RX_NUM_OF_CONVERTERS 1 {122.88} {122.88} \
"$ad_hdl_dir/library/util_fir_int/coefile_int.coe"
# adc-os peripherals
ad_ip_instance axi_clkgen axi_ad9371_rx_os_clkgen
@ -230,15 +238,31 @@ ad_connect axi_ad9371_tx_jesd/tx_data tx_ad9371_tpl_core/link
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_tx_upack/clk
ad_connect ad9371_tx_device_clk_rstgen/peripheral_reset util_ad9371_tx_upack/reset
ad_connect tx_ad9371_tpl_core/dac_valid_0 util_ad9371_tx_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect util_ad9371_tx_upack/fifo_rd_data_$i tx_ad9371_tpl_core/dac_data_$i
ad_connect tx_ad9371_tpl_core/dac_enable_$i util_ad9371_tx_upack/enable_$i
}
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
ad_connect ad9371_tx_device_clk_rstgen/peripheral_reset axi_ad9371_dacfifo/dac_rst
ad_connect tx_fir_interpolator/aclk axi_ad9371_tx_clkgen/clk_0
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect tx_ad9371_tpl_core/dac_enable_$i tx_fir_interpolator/dac_enable_$i
ad_connect tx_ad9371_tpl_core/dac_valid_$i tx_fir_interpolator/dac_valid_$i
ad_connect util_ad9371_tx_upack/fifo_rd_data_$i tx_fir_interpolator/data_in_${i}
ad_connect util_ad9371_tx_upack/enable_$i tx_fir_interpolator/enable_out_${i}
ad_connect tx_fir_interpolator/data_out_${i} tx_ad9371_tpl_core/dac_data_$i
}
ad_ip_instance util_vector_logic logic_or [list \
C_OPERATION {or} \
C_SIZE 1]
ad_connect logic_or/Op1 tx_fir_interpolator/valid_out_0
ad_connect logic_or/Op2 tx_fir_interpolator/valid_out_2
ad_connect logic_or/Res util_ad9371_tx_upack/fifo_rd_en
ad_connect tx_fir_interpolator/active dac_fir_filter_active
# TODO: Add streaming AXI interface for DAC FIFO
ad_connect util_ad9371_tx_upack/s_axis_valid VCC
ad_connect util_ad9371_tx_upack/s_axis_ready axi_ad9371_dacfifo/dac_valid
@ -264,13 +288,22 @@ ad_connect axi_ad9371_rx_jesd/rx_data_tvalid rx_ad9371_tpl_core/link_valid
ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_rx_cpack/clk
ad_connect ad9371_rx_device_clk_rstgen/peripheral_reset util_ad9371_rx_cpack/reset
ad_connect rx_ad9371_tpl_core/adc_valid_0 util_ad9371_rx_cpack/fifo_wr_en
ad_connect rx_fir_decimator/aclk axi_ad9371_rx_clkgen/clk_0
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_ad9371_tpl_core/adc_enable_$i util_ad9371_rx_cpack/enable_$i
ad_connect rx_ad9371_tpl_core/adc_data_$i util_ad9371_rx_cpack/fifo_wr_data_$i
ad_connect rx_ad9371_tpl_core/adc_valid_$i rx_fir_decimator/valid_in_$i
ad_connect rx_ad9371_tpl_core/adc_enable_$i rx_fir_decimator/enable_in_$i
ad_connect rx_ad9371_tpl_core/adc_data_$i rx_fir_decimator/data_in_${i}
ad_connect rx_fir_decimator/enable_out_$i util_ad9371_rx_cpack/enable_$i
ad_connect rx_fir_decimator/data_out_${i} util_ad9371_rx_cpack/fifo_wr_data_$i
}
ad_connect rx_fir_decimator/valid_out_0 util_ad9371_rx_cpack/fifo_wr_en
ad_connect rx_ad9371_tpl_core/adc_dovf util_ad9371_rx_cpack/fifo_wr_overflow
ad_connect rx_fir_decimator/active adc_fir_filter_active
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
ad_connect util_ad9371_rx_cpack/packed_fifo_wr axi_ad9371_rx_dma/fifo_wr
ad_connect $sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn

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@ -8,6 +8,8 @@ adi_project_files adrv9371x_kcu105 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_bus_mux.v" \
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
"$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" \
"$ad_hdl_dir/projects/common/kcu105/kcu105_system_lutram_constr.xdc" ]

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@ -229,6 +229,8 @@ module system_top (
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[60]),
.adc_fir_filter_active (gpio_o[61]),
.dac_fir_filter_active (gpio_o[62]),
.c0_ddr4_act_n (ddr4_act_n),
.c0_ddr4_adr (ddr4_addr),
.c0_ddr4_ba (ddr4_ba),

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@ -10,6 +10,8 @@ adi_project_files adrv9371x_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_bus_mux.v" \
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]

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@ -238,6 +238,8 @@ module system_top (
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[60]),
.adc_fir_filter_active (gpio_o[61]),
.dac_fir_filter_active (gpio_o[62]),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),

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@ -8,6 +8,8 @@ adi_project_files adrv9371x_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_bus_mux.v" \
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run adrv9371x_zcu102

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@ -191,6 +191,8 @@ module system_top (
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[60]),
.adc_fir_filter_active (gpio_o[61]),
.dac_fir_filter_active (gpio_o[62]),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),