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axi_dmac: Remove backpressure from the source pipeline 

Data is gated on the source side interface and not let into the pipeline if
there is no space available inside the store and forward memory.

This means whenever data is let into the pipeline space is available and
backpressure wont be asserted. Remove the backpressure signals altogether
to simplify the design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-05-14 10:16:04 +02:00 committed by Lars-Peter Clausen
parent 7d643e216a
commit 44e09f58cd
6 changed files with 19 additions and 41 deletions
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13
library/axi_dmac/axi_dmac_burst_memory.v
View File

@ -44,7 +44,6 @@ module axi_dmac_burst_memory #(
input src_reset,
input src_data_valid,
output src_data_ready,
input [DATA_WIDTH_SRC-1:0] src_data,
input src_data_last,
@ -108,7 +107,6 @@ reg [ID_WIDTH-1:0] src_id_next;
reg [ID_WIDTH-1:0] src_id = 'h0;
reg src_id_reduced_msb = 1'b0;
reg [BURST_LEN_WIDTH-1:0] src_beat_counter = 'h00;
reg src_mem_data_ready = 1'b0;
reg [ID_WIDTH-1:0] dest_id_next = 'h0;
reg dest_id_reduced_msb_next = 1'b0;
@ -157,7 +155,7 @@ end else begin
assign dest_id_reduced = dest_id_reduced_msb;
end endgenerate
assign src_beat = src_mem_data_valid & src_mem_data_ready;
assign src_beat = src_mem_data_valid;
assign src_last_beat = src_beat & src_mem_data_last;
assign src_waddr = {src_id_reduced,src_beat_counter};
@ -171,13 +169,6 @@ always @(*) begin
end
end
always @(posedge src_clk) begin
/* Ready if there is room for at least one full burst. */
src_mem_data_ready <= (src_id_next[ID_WIDTH-1] == src_dest_id[ID_WIDTH-1] ||
src_id_next[ID_WIDTH-2] == src_dest_id[ID_WIDTH-2] ||
src_id_next[ID_WIDTH-3:0] != src_dest_id[ID_WIDTH-3:0]);
end
always @(posedge src_clk) begin
if (src_reset == 1'b1) begin
src_id <= 'h00;
@ -303,12 +294,10 @@ axi_dmac_resize_src #(
.reset (src_reset),
.src_data_valid (src_data_valid),
.src_data_ready (src_data_ready),
.src_data (src_data),
.src_data_last (src_data_last),
.mem_data_valid (src_mem_data_valid),
.mem_data_ready (src_mem_data_ready),
.mem_data (src_mem_data),
.mem_data_last (src_mem_data_last)
);

18
library/axi_dmac/axi_dmac_resize_src.v
View File

@ -46,19 +46,16 @@ module axi_dmac_resize_src #(
input reset,
input src_data_valid,
output src_data_ready,
input [DATA_WIDTH_SRC-1:0] src_data,
input src_data_last,
output mem_data_valid,
input mem_data_ready,
output [DATA_WIDTH_MEM-1:0] mem_data,
output mem_data_last
);
generate if (DATA_WIDTH_SRC == DATA_WIDTH_MEM) begin
assign mem_data_valid = src_data_valid;
assign src_data_ready = mem_data_ready;
assign mem_data = src_data;
assign mem_data_last = src_data_last;
end else begin
@ -74,10 +71,10 @@ end else begin
if (reset == 1'b1) begin
valid <= 1'b0;
mask <= 'h1;
end else if (src_data_valid == 1'b1 && src_data_ready == 1'b1) begin
end else if (src_data_valid == 1'b1) begin
valid <= mask[RATIO-1];
mask <= {mask[RATIO-2:0],mask[RATIO-1]};
end else if (mem_data_ready == 1'b1) begin
end else begin
valid <= 1'b0;
end
end
@ -85,17 +82,14 @@ end else begin
integer i;
always @(posedge clk) begin
if (src_data_ready == 1'b1) begin
for (i = 0; i < RATIO; i = i+1) begin
if (mask[i] == 1'b1) begin
data[i*DATA_WIDTH_SRC+:DATA_WIDTH_SRC] <= src_data;
end
for (i = 0; i < RATIO; i = i+1) begin
if (mask[i] == 1'b1) begin
data[i*DATA_WIDTH_SRC+:DATA_WIDTH_SRC] <= src_data;
end
last <= src_data_last;
end
last <= src_data_last;
end
assign src_data_ready = ~valid | mem_data_ready;
assign mem_data_valid = valid;
assign mem_data = data;
assign mem_data_last = last;

12
library/axi_dmac/request_arb.v
View File

@ -256,11 +256,9 @@ wire [ID_WIDTH-1:0] src_data_request_id;
wire [ID_WIDTH-1:0] src_response_id;
wire src_valid;
wire src_ready;
wire [DMA_DATA_WIDTH_SRC-1:0] src_data;
wire src_last;
wire src_fifo_valid;
wire src_fifo_ready;
wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data;
wire src_fifo_last;
@ -552,7 +550,6 @@ dmac_src_mm_axi #(
.address_eot(src_address_eot),
.fifo_valid(src_valid),
.fifo_ready(src_ready),
.fifo_data(src_data),
.fifo_last(src_last),
@ -623,7 +620,6 @@ dmac_src_axi_stream #(
.eot(src_eot),
.fifo_valid(src_valid),
.fifo_ready(src_ready),
.fifo_data(src_data),
.fifo_last(src_last),
@ -679,7 +675,6 @@ dmac_src_fifo_inf #(
.eot(src_eot),
.fifo_valid(src_valid),
.fifo_ready(src_ready),
.fifo_data(src_data),
.fifo_last(src_last),
@ -753,15 +748,15 @@ sync_bits #(
axi_register_slice #(
.DATA_WIDTH(DMA_DATA_WIDTH_SRC + 1),
.FORWARD_REGISTERED(AXI_SLICE_SRC),
.BACKWARD_REGISTERED(AXI_SLICE_SRC)
.BACKWARD_REGISTERED(0)
) i_src_slice (
.clk(src_clk),
.resetn(src_resetn),
.s_axi_valid(src_valid),
.s_axi_ready(src_ready),
.s_axi_ready(),
.s_axi_data({src_data,src_last}),
.m_axi_valid(src_fifo_valid),
.m_axi_ready(src_fifo_ready),
.m_axi_ready(1'b1), /* No backpressure */
.m_axi_data({src_fifo_data,src_fifo_last})
);
@ -775,7 +770,6 @@ axi_dmac_burst_memory #(
.src_clk(src_clk),
.src_reset(~src_resetn),
.src_data_valid(src_fifo_valid),
.src_data_ready(src_fifo_ready),
.src_data(src_fifo_data),
.src_data_last(src_fifo_last),

11
library/axi_dmac/src_axi_mm.v
View File

@ -67,7 +67,6 @@ module dmac_src_mm_axi #(
input address_eot,
output fifo_valid,
input fifo_ready,
output [DMA_DATA_WIDTH-1:0] fifo_data,
output fifo_last,
@ -133,7 +132,6 @@ dmac_address_generator #(
);
assign fifo_valid = m_axi_rvalid;
assign m_axi_rready = fifo_ready;
assign fifo_data = m_axi_rdata;
assign fifo_last = m_axi_rlast;
@ -146,12 +144,17 @@ assign fifo_last = m_axi_rlast;
always @(posedge m_axi_aclk) begin
if (m_axi_aresetn == 1'b0) begin
id <= 'h00;
end else if (m_axi_rvalid == 1'b1 && m_axi_rready == 1'b1 &&
m_axi_rlast == 1'b1) begin
end else if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin
id <= inc_id(id);
end
end
/*
* We won't be receiving data before we've requested it and we won't request
* data unless there is room in the store-and-forward memory.
*/
assign m_axi_rready = 1'b1;
/*
* We need to complete all bursts for which an address has been put onto the
* AXI-MM interface.

3
library/axi_dmac/src_axi_stream.v
View File

@ -57,7 +57,6 @@ module dmac_src_axi_stream #(
input s_axis_last,
output s_axis_xfer_req,
input fifo_ready,
output fifo_valid,
output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
output fifo_last,
@ -141,7 +140,7 @@ dmac_data_mover # (
.s_axi_ready(data_ready),
.s_axi_valid(data_valid),
.s_axi_data(data),
.m_axi_ready(fifo_ready),
.m_axi_ready(1'b1),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last(fifo_last)

3
library/axi_dmac/src_fifo_inf.v
View File

@ -55,7 +55,6 @@ module dmac_src_fifo_inf #(
input sync,
output xfer_req,
input fifo_ready,
output fifo_valid,
output [DATA_WIDTH-1:0] fifo_data,
output fifo_last,
@ -117,7 +116,7 @@ dmac_data_mover # (
.s_axi_ready(ready),
.s_axi_valid(sync_valid),
.s_axi_data(din),
.m_axi_ready(fifo_ready),
.m_axi_ready(1'b1),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last(fifo_last)