diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index b299190fd..27a186a03 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v index fd51c0a0f..9623a96f4 100644 --- a/library/axi_ad9434/axi_ad9434.v +++ b/library/axi_ad9434/axi_ad9434.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -38,7 +38,6 @@ module axi_ad9434 #( parameter ID = 0, - parameter FPGA_TECHNOLOGY = 0, parameter FPGA_FAMILY = 0, parameter SPEED_GRADE = 0, diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v index fa10d4765..67e858ed5 100644 --- a/library/axi_ad9434/axi_ad9434_if.v +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -195,7 +195,7 @@ module axi_ad9434_if #( // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up always @(posedge adc_div_clk) begin - if(adc_rst == 1'b1) begin + if (adc_rst == 1'b1) begin adc_status_m1 <= 1'b0; adc_status <= 1'b0; end else begin diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v index 251baf3d9..31737ac98 100644 --- a/library/axi_ad9684/axi_ad9684_if.v +++ b/library/axi_ad9684/axi_ad9684_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v index a0898b2ec..0db33caef 100644 --- a/library/axi_ad9739a/axi_ad9739a_if.v +++ b/library/axi_ad9739a/axi_ad9739a_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_ad9783/axi_ad9783_if.v b/library/axi_ad9783/axi_ad9783_if.v index 4e0bb2e12..f12e85958 100755 --- a/library/axi_ad9783/axi_ad9783_if.v +++ b/library/axi_ad9783/axi_ad9783_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2021 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_rx.v b/library/axi_adrv9001/adrv9001_rx.v index 65db4cb93..8de38a1a4 100644 --- a/library/axi_adrv9001/adrv9001_rx.v +++ b/library/axi_adrv9001/adrv9001_rx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/adrv9001_tx.v b/library/axi_adrv9001/adrv9001_tx.v index 3551affa5..830586283 100644 --- a/library/axi_adrv9001/adrv9001_tx.v +++ b/library/axi_adrv9001/adrv9001_tx.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001.v b/library/axi_adrv9001/axi_adrv9001.v index 9d6704e0e..d77145f4a 100644 --- a/library/axi_adrv9001/axi_adrv9001.v +++ b/library/axi_adrv9001/axi_adrv9001.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are diff --git a/library/axi_adrv9001/axi_adrv9001_if.v b/library/axi_adrv9001/axi_adrv9001_if.v index fb7dd3380..2cde66176 100644 --- a/library/axi_adrv9001/axi_adrv9001_if.v +++ b/library/axi_adrv9001/axi_adrv9001_if.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -205,16 +205,16 @@ module axi_adrv9001_if #( wire rx_ssi_sync_out; - adrv9001_rx - #(.CMOS_LVDS_N (CMOS_LVDS_N), - .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), - .NUM_LANES (NUM_LANES), - .DRP_WIDTH (DRP_WIDTH), - .IODELAY_CTRL (IODELAY_CTRL), - .IODELAY_ENABLE (IODELAY_ENABLE), - .USE_BUFG (RX_USE_BUFG), - .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"}) - ) i_rx_1_phy ( + adrv9001_rx #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .NUM_LANES (NUM_LANES), + .DRP_WIDTH (DRP_WIDTH), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_ENABLE (IODELAY_ENABLE), + .USE_BUFG (RX_USE_BUFG), + .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"}) + ) i_rx_1_phy ( .rx_dclk_in_n_NC (rx1_dclk_in_n_NC), .rx_dclk_in_p_dclk_in (rx1_dclk_in_p_dclk_in), .rx_idata_in_n_idata0 (rx1_idata_in_n_idata0), @@ -247,8 +247,7 @@ module axi_adrv9001_if #( .mssi_sync (mssi_sync), .ssi_sync_out (rx_ssi_sync_out), .ssi_sync_in (rx_ssi_sync_out), - .ssi_rst (adc_1_ssi_rst) - ); + .ssi_rst (adc_1_ssi_rst)); adrv9001_rx_link #( .CMOS_LVDS_N (CMOS_LVDS_N) @@ -272,16 +271,16 @@ module axi_adrv9001_if #( .rx_symb_8_16b (rx1_symb_8_16b)); generate if (DISABLE_RX2_SSI == 0) begin - adrv9001_rx - #(.CMOS_LVDS_N (CMOS_LVDS_N), - .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), - .NUM_LANES (NUM_LANES), - .DRP_WIDTH (DRP_WIDTH), - .IODELAY_CTRL (0), - .IODELAY_ENABLE (IODELAY_ENABLE), - .USE_BUFG (RX_USE_BUFG), - .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"}) - ) i_rx_2_phy ( + adrv9001_rx #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .NUM_LANES (NUM_LANES), + .DRP_WIDTH (DRP_WIDTH), + .IODELAY_CTRL (0), + .IODELAY_ENABLE (IODELAY_ENABLE), + .USE_BUFG (RX_USE_BUFG), + .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"}) + ) i_rx_2_phy ( .rx_dclk_in_n_NC (rx2_dclk_in_n_NC), .rx_dclk_in_p_dclk_in (rx2_dclk_in_p_dclk_in), .rx_idata_in_n_idata0 (rx2_idata_in_n_idata0), @@ -312,8 +311,7 @@ module axi_adrv9001_if #( .mssi_sync (1'b0), .ssi_sync_out (), .ssi_sync_in (rx_ssi_sync_out), - .ssi_rst (adc_2_ssi_rst) - ); + .ssi_rst (adc_2_ssi_rst)); adrv9001_rx_link #( .CMOS_LVDS_N (CMOS_LVDS_N) diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v index d8377f5c9..c9e39b436 100644 --- a/library/xilinx/common/ad_serdes_clk.v +++ b/library/xilinx/common/ad_serdes_clk.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -40,6 +40,8 @@ module ad_serdes_clk #( parameter FPGA_TECHNOLOGY = 0, parameter DDR_OR_SDR_N = 1, + // single ended - 0 + // differential - 1 parameter CLKIN_DS_OR_SE_N = 1, parameter SERDES_FACTOR = 8, parameter MMCM_OR_BUFR_N = 1, @@ -128,7 +130,7 @@ module ad_serdes_clk #( .up_drp_rdata (up_drp_rdata[15:0]), .up_drp_ready (up_drp_ready), .up_drp_locked (up_drp_locked)); - end + end endgenerate generate diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v index ca7112ea3..f483108bb 100644 --- a/library/xilinx/common/ad_serdes_in.v +++ b/library/xilinx/common/ad_serdes_in.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -36,6 +36,7 @@ `timescale 1ps/1ps module ad_serdes_in #( + parameter FPGA_TECHNOLOGY = 0, parameter CMOS_LVDS_N = 0, parameter DDR_OR_SDR_N = 0, @@ -97,13 +98,17 @@ module ad_serdes_in #( FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" : FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE" : "UNSUPPORTED"; + // internal registers + + reg [6:0] serdes_rst_seq; // internal signals - wire [(DATA_WIDTH-1):0] data_in_ibuf_s; - wire [(DATA_WIDTH-1):0] data_in_idelay_s; - wire [(DATA_WIDTH-1):0] data_shift1_s; - wire [(DATA_WIDTH-1):0] data_shift2_s; + wire [(DATA_WIDTH-1):0] data_in_ibuf_s; + wire [(DATA_WIDTH-1):0] data_in_idelay_s; + wire [(DATA_WIDTH-1):0] data_shift1_s; + wire [(DATA_WIDTH-1):0] data_shift2_s; + wire serdes_rst = serdes_rst_seq[6]; // delay controller @@ -127,18 +132,18 @@ module ad_serdes_in #( genvar l_inst; generate - for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io - if (CMOS_LVDS_N == 0) begin - IBUFDS i_ibuf ( - .I (data_in_p[l_inst]), - .IB (data_in_n[l_inst]), - .O (data_in_ibuf_s[l_inst])); - end else begin - IBUF i_ibuf ( - .I (data_in_p[l_inst]), - .O (data_in_ibuf_s[l_inst])); - end - end + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io + if (CMOS_LVDS_N == 0) begin + IBUFDS i_ibuf ( + .I (data_in_p[l_inst]), + .IB (data_in_n[l_inst]), + .O (data_in_ibuf_s[l_inst])); + end else begin + IBUF i_ibuf ( + .I (data_in_p[l_inst]), + .O (data_in_ibuf_s[l_inst])); + end + end endgenerate // bypass IDELAY @@ -149,44 +154,44 @@ module ad_serdes_in #( end endgenerate - reg [6:0] serdes_rst_seq; - wire serdes_rst = serdes_rst_seq [6]; - - always @ (posedge div_clk) - begin - if (rst) serdes_rst_seq [6:0] <= 7'b0001110; - else serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + always @ (posedge div_clk) begin + if (rst) begin + serdes_rst_seq [6:0] <= 7'b0001110; + end else begin + serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + end end // idelay + iserdes - generate if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + generate + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data if (IODELAY_ENABLE == 1) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("IDATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .IDELAY_TYPE ("VAR_LOAD"), - .IDELAY_VALUE (0), - .REFCLK_FREQUENCY (REFCLK_FREQUENCY), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA") - ) i_idelay ( - .CE (1'b0), - .INC (1'b0), - .DATAIN (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .IDATAIN (data_in_ibuf_s[l_inst]), - .DATAOUT (data_in_idelay_s[l_inst]), - .LD (up_dld[l_inst]), - .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), - .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH])); + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .IDELAY_TYPE ("VAR_LOAD"), + .IDELAY_VALUE (0), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA") + ) i_idelay ( + .CE (1'b0), + .INC (1'b0), + .DATAIN (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .IDATAIN (data_in_ibuf_s[l_inst]), + .DATAOUT (data_in_idelay_s[l_inst]), + .LD (up_dld[l_inst]), + .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), + .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH])); end ISERDESE2 #( @@ -241,8 +246,8 @@ module ad_serdes_in #( end endgenerate - generate if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin - + generate + if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data wire div_dld; @@ -257,34 +262,34 @@ module ad_serdes_in #( .out_event (div_dld)); if (IODELAY_ENABLE == 1) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYE3 #( - .CASCADE ("NONE"), // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) - .DELAY_FORMAT ("TIME"), // Units of the DELAY_VALUE (COUNT, TIME) - .DELAY_SRC ("IDATAIN"), // Delay input (DATAIN, IDATAIN) - .DELAY_TYPE ("VAR_LOAD"), // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) - .DELAY_VALUE (0), // Input delay value setting - .IS_CLK_INVERTED (1'b0), // Optional inversion for CLK - .IS_RST_INVERTED (1'b0), // Optional inversion for RST - .REFCLK_FREQUENCY (500.0), // IDELAYCTRL clock input frequency in MHz (200.0-2667.0) - .SIM_DEVICE (SIM_DEVICE), // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, - // ULTRASCALE_PLUS_ES2) - .UPDATE_MODE ("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) - ) i_idelay ( - .CASC_OUT (), // 1-bit output: Cascade delay output to ODELAY input cascade - .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit output: Counter value output - .DATAOUT (data_in_idelay_s[l_inst]), // 1-bit output: Delayed data output - .CASC_IN (1'b0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT - .CASC_RETURN (1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT - .CE (1'b0), // 1-bit input: Active high enable increment/decrement input - .CLK (div_clk), // 1-bit input: Clock input - .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit input: Counter value input - .DATAIN (1'b0), // 1-bit input: Data input from the logic - .EN_VTC (en_vtc), // 1-bit input: Keep delay constant over VT - .IDATAIN (data_in_ibuf_s[l_inst]), // 1-bit input: Data input from the IOBUF - .INC (1'b0), // 1-bit input: Increment / Decrement tap delay input - .LOAD (ld_cnt), // 1-bit input: Load DELAY_VALUE input - .RST (rst)); // 1-bit input: Asynchronous Reset to the DELAY_VALUE + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE3 #( + .CASCADE ("NONE"), // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) + .DELAY_FORMAT ("TIME"), // Units of the DELAY_VALUE (COUNT, TIME) + .DELAY_SRC ("IDATAIN"), // Delay input (DATAIN, IDATAIN) + .DELAY_TYPE ("VAR_LOAD"), // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) + .DELAY_VALUE (0), // Input delay value setting + .IS_CLK_INVERTED (1'b0), // Optional inversion for CLK + .IS_RST_INVERTED (1'b0), // Optional inversion for RST + .REFCLK_FREQUENCY (500.0), // IDELAYCTRL clock input frequency in MHz (200.0-2667.0) + .SIM_DEVICE (SIM_DEVICE), // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, + // ULTRASCALE_PLUS_ES2) + .UPDATE_MODE ("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) + ) i_idelay ( + .CASC_OUT (), // 1-bit output: Cascade delay output to ODELAY input cascade + .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit output: Counter value output + .DATAOUT (data_in_idelay_s[l_inst]), // 1-bit output: Delayed data output + .CASC_IN (1'b0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT + .CASC_RETURN (1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT + .CE (1'b0), // 1-bit input: Active high enable increment/decrement input + .CLK (div_clk), // 1-bit input: Clock input + .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit input: Counter value input + .DATAIN (1'b0), // 1-bit input: Data input from the logic + .EN_VTC (en_vtc), // 1-bit input: Keep delay constant over VT + .IDATAIN (data_in_ibuf_s[l_inst]), // 1-bit input: Data input from the IOBUF + .INC (1'b0), // 1-bit input: Increment / Decrement tap delay input + .LOAD (ld_cnt), // 1-bit input: Load DELAY_VALUE input + .RST (rst)); // 1-bit input: Asynchronous Reset to the DELAY_VALUE end always @(posedge div_clk) begin @@ -329,5 +334,4 @@ module ad_serdes_in #( end end endgenerate - endmodule diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v index f28002d51..3e5322234 100644 --- a/library/xilinx/common/ad_serdes_out.v +++ b/library/xilinx/common/ad_serdes_out.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -76,26 +76,30 @@ module ad_serdes_out #( FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" : "UNSUPPORTED"; - // internal signals - - wire [(DATA_WIDTH-1):0] data_out_s; - wire [(DATA_WIDTH-1):0] serdes_shift1_s; - wire [(DATA_WIDTH-1):0] serdes_shift2_s; - wire [(DATA_WIDTH-1):0] data_t; - wire buffer_disable; - - assign data_out_se = data_out_s; - - assign buffer_disable = ~data_oe; - // instantiations + // internal registers reg [6:0] serdes_rst_seq; - wire serdes_rst = serdes_rst_seq [6]; - always @ (posedge div_clk) - begin - if (rst) serdes_rst_seq [6:0] <= 7'b0001110; - else serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + // internal signals + + wire [(DATA_WIDTH-1):0] data_out_s; + wire [(DATA_WIDTH-1):0] serdes_shift1_s; + wire [(DATA_WIDTH-1):0] serdes_shift2_s; + wire [(DATA_WIDTH-1):0] data_t; + wire buffer_disable; + wire serdes_rst = serdes_rst_seq[6]; + + // instantiations + + assign data_out_se = data_out_s; + assign buffer_disable = ~data_oe; + + always @ (posedge div_clk) begin + if (rst) begin + serdes_rst_seq [6:0] <= 7'b0001110; + end else begin + serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + end end // transmit data path: oserdes -> obuf @@ -107,7 +111,7 @@ module ad_serdes_out #( // oserdes if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin - OSERDESE2 #( + OSERDESE2 #( .DATA_RATE_OQ (DR_OQ_DDR), .DATA_RATE_TQ ("SDR"), .DATA_WIDTH (SERDES_FACTOR), @@ -144,7 +148,7 @@ module ad_serdes_out #( end if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin - OSERDESE3 #( + OSERDESE3 #( .DATA_WIDTH (SERDES_FACTOR), .SIM_DEVICE (SIM_DEVICE) ) i_serdes ( @@ -172,17 +176,12 @@ module ad_serdes_out #( .I (data_out_s[l_inst]), .O (data_out_p[l_inst]), .OB (data_out_n[l_inst])); - end else begin - OBUFT i_obuf ( .T (data_t[l_inst]), .I (data_out_s[l_inst]), .O (data_out_p[l_inst])); - end - end endgenerate - endmodule